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TMS320C6201 Silicon Errata
2
Changes to the TMS320C6201 Data Sheet (literature number SPRS051)
Table 2. Timing Requirements for Interrupt Response Cycles
NO.
NO
4
t d(CKO2L-IACKV)
5
t d(CKO2L-INUMV)
6
t d(CKO2L-INUMIV)
NO.
NO.
1
T c(TCK)
4
T h(TCKH-TDIV)
Figure 2. SBSRAM Read Timing (1/2 Rate SSCLK) (See Note)
SSCLK
CE
BE_ [3:0]
EA [21:2]
ED [31:0]
SSADS
SSOE
SSWE
NOTE: The CEx output setup and hold times are specified to be accurate relative to the clock cycle to which they are referenced, since
these timings are specified as minimums. However, the CE output setup and hold time may be greater than that shown
in the data sheet in multiples of P ns. In other words, for output setup time, the CEx transition from high to low may happen P,
2P,
, or nP ns before the time specified by the data sheet. Similarly, for output hold time, the CEx low-to-high transition may
happen P, 2P,
, or nP ns after the time specified by the data sheet. This is indicated by the period of uncertainty for specs 1
and 2 in Figure 2, and Figure 3.
Delay time, CLKOUT2 low to IACK valid
Delay time, CLKOUT2 low to INUMx valid
Delay time, CLKOUT2 low to INUMx invalid
Table 3. JTAG Test-Port Timing
Cycle time, TCK
Hold time, TDI/TMS/TRST valid after TCK high
1
3
BE1
5
A1
9
11
4
BE2
BE3
BE4
6
A2
A3
A4
8
7
Q1
Q2
Q3
10
SPRZ153
C6201B
UNIT
UNIT
MIN
MAX
–4
6
ns
6
ns
–4
ns
C6201,
C6201B
UNIT
UNIT
MIN
MAX
50
ns
9
ns
2
Q4
12
6
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