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TMS320C6201 Silicon Errata
Advisory 2.0.5
Revision(s) Affected:
Details:
Workaround:
Advisory 2.0.7
Revision(s) Affected:
Details:
Workaround:
Advisory 2.0.8
Revision(s) Affected:
Details:
Workaround:
Data Access: Parallel Accesses to EMIF or Internal Peripheral Bus Location
2.0
Parallel read and write accesses to the same EMIF or internal peripheral bus location are
sequenced incorrectly when:
A load and store are in the same execute packet and either
–
The addresses both point to off-chip memory through the EMIF, and the load has
a destination register in side A (therefore, the store would have a source register
in side B). Or
–
The addresses both point to the peripheral bus, and the load has a destination
register in side B (therefore, the store would have a source register in side A).
When these conditions occur, the store occurs first rather than the load. In general, this will
only cause an error if both the load and store addresses are the same. This bug does not
occur if both accesses are to internal data memory. (Internal Reference Number 3087)
Avoid loading and storing the same address on the same cycle.
2.0
Fields in Bits 15:14 of the EMIF CE Space Control registers are writable. They should be read
only and have a 0 value. Bits 5:4 of the EMIF SDRAM Control register are 11b rather than 0.
(Internal Reference Number s 3248 and 3283)
Mask these values if 0s are expected and to only write 0s to reserved fields.
EMIF: SDRAM Refresh/DCAB Not Performed Prior to HOLD Request Being Granted
2.0
SDRAM is left in the current state when an external HOLD is granted. SDRAM refresh/DCAB
is necessary if an interface to a shared memory external SDRAM controller is desired.
(Internal Reference Number 3249)
Make sure the external controller performs a refresh/DCAB before performing SDRAM
accesses.
EMIF: Reserved Fields Have Incorrect Values
SPRZ153
Sequenced Wrong
25
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