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Texas Instruments TMS320C64x DSP Manuals
Manuals and User Guides for Texas Instruments TMS320C64x DSP. We have
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Texas Instruments TMS320C64x DSP manuals available for free PDF download: Reference Manual, Programmer's Reference Manual
Texas Instruments TMS320C64x DSP Reference Manual (306 pages)
DSP Video Port/VCXO Interpolated Control (VIC) Port
Brand:
Texas Instruments
| Category:
Signal Processors
| Size: 1.91 MB
Table of Contents
Read this First
3
Table of Contents
5
Overview
18
Video Port
19
Video Port Block Diagram
21
Video Port FIFO
22
DMA Interface
22
Video Capture FIFO Configurations
23
BT.656 Video Capture FIFO Configuration
23
Bit Raw Video Capture and TSI Video Capture FIFO Configuration
24
Y/C Video Capture FIFO Configuration
25
Video Display FIFO Configurations
26
Bit Raw Video Capture FIFO Configuration
26
BT.656 Video Display FIFO Configuration
26
Bit Raw Video Display FIFO Configuration
27
Bit Locked Raw Video Display FIFO Configuration
28
Bit Raw Video Display FIFO Configuration
28
Video Port Registers
29
Y/C Video Display FIFO Configuration
29
Video Port Pin Mapping
30
Video Capture Signal Mapping
30
Video Display Signal Mapping
31
VDIN Bus Usage for Capture Modes
32
VDIN Data Bus Usage for Capture Modes
32
VDOUT Data Bus Usage for Display Modes
33
Video Port
34
Chapter 2
35
Reset Operation
35
Power-On Reset
35
Peripheral Bus Reset
35
Software Port Reset
36
Capture Channel Reset
36
Display Channel Reset
37
Interrupt Operation
38
DMA Operation
39
Capture DMA Event Generation
39
Capture DMA Event Generation Flow Diagram
40
Display DMA Event Generation
41
Display DMA Event Generation Flow Diagram
42
DMA Size and Threshold Restrictions
43
DMA Interface Operation
44
Clocks
45
Video Port Functional Clocks
45
FIFO Size
46
Video Port Functionality Subsets
45
Data Bus Width
45
Video Capture Throughput
46
Y/C Video Capture FIFO Capacity
47
Video Display Throughput
48
Raw Video Display FIFO Capacity
48
Video Port Throughput and Latency
46
Video Port Control Registers
49
Video Port Control Register (VPCTL)
50
Video Port Control Register (VPCTL) Field Descriptions
50
Video Port Operating Mode Selection
52
Video Port Status Register (VPSTAT)
53
Video Port Status Register (VPSTAT) Field Descriptions
53
Video Port Interrupt Enable Register (VPIE)
54
Video Port Interrupt Enable Register (VPIE) Field Descriptions
54
Video Port Interrupt Status Register (VPIS)
57
Video Port Interrupt Status Register (VPIS) Field Descriptions
57
Video Capture Mode Selection
63
Video Capture Port
63
Video Capture Mode Selection
64
BT.656 Video Capture Mode
65
BT.656 Capture Channels
65
BT.656 Timing Reference Codes
66
BT.656 Video Timing Reference Codes
66
BT.656 Protection Bits
67
Error Correction by Protection Bits
67
BT.656 Image Window and Capture
68
Common Video Source Parameters
69
BT.656 Data Sampling
70
BT.656 FIFO Packing
71
Video Capture Parameters
69
Bit BT.656 FIFO Packing
71
Bit BT.656 FIFO Packing
72
Bit BT.656 Dense FIFO Packing
73
Y/C Video Capture Mode
74
Y/C Capture Channels
74
Y/C Timing Reference Codes
74
Y/C Image Window and Capture
75
Y/C FIFO Packing
76
Bit Y/C FIFO Packing
76
Bit Y/C FIFO Packing
77
Bit Y/C Dense FIFO Packing
78
BT.656 and Y/C Mode Field and Frame Operation
79
Capture Determination and Notification
79
BT.656 and Y/C Mode Capture Operation
80
Vertical Synchronization
81
Vertical Synchronization Programming
82
VCOUNT Operation Example (EXC = 0)
83
Horizontal Synchronization Programming
84
HCOUNT Operation Example (EXC = 0)
85
HCOUNT Operation Example (EXC = 1)
85
Field Identification Programming
86
Short and Long Field Detect
87
Field 1 Detection Timing
87
Video Input Filtering
88
Input Filter Mode Selection
88
Chrominance Resampling
89
Chrominance Resampling Operation
89
Scaling Operation
89
Scaled Chrominance Resampled Filtering
90
Scaled Co-Sited Filtering
90
Edge Pixel Replication
91
Capture Window Not Requiring Edge Pixel Replication
92
Ancillary Data Capture
93
Raw Data Capture Mode
94
Raw Data Capture Notification
94
Raw Data FIFO Packing
95
Raw Data Mode Capture Operation
95
Bit Raw Data FIFO Packing
96
Bit Dense Raw Data FIFO Packing
97
Bit Raw Data FIFO Packing
97
Bit Raw Data FIFO Packing
98
TSI Capture Mode
99
TSI Capture Features
99
TSI Data Capture
99
TSI Capture Error Detection
100
Synchronizing the System Clock
100
Parallel TSI Capture
100
Program Clock Reference (PCR) Header Format
101
System Time Clock Counter Operation
101
TSI Data Capture Notification
102
TSI Capture Mode Operation
102
Writing to the FIFO
103
TSI FIFO Packing
103
TSI Timestamp Format (Little Endian)
103
Reading from the FIFO
104
Capture Line Boundary Conditions
104
TSI Timestamp Format (Big Endian)
104
Capture Line Boundary Example
105
Capturing Video in BT.656 or Y/C Mode
106
Handling FIFO Overrun in BT.656 or Y/C Mode
107
Capturing Video in Raw Data Mode
108
Handling FIFO Overrun Condition in Raw Data Mode
109
Capturing Data in TSI Capture Mode
109
Handling FIFO Overrun Condition in TSI Capture Mode
110
Video Capture Registers
111
Video Capture Control Registers
111
Video Capture Channel X Status Register (VCASTAT, VCBSTAT)
112
Video Capture Channel X Status Register (Vcxstat) Field Descriptions
113
Field Descriptions
113
Field Descriptions
114
Video Capture Channel a Control Register (VCACTL)
115
Video Capture Channel a Control Register (VCACTL) Field Descriptions
115
Field Descriptions
115
Field Descriptions
116
Field Descriptions
117
Field Descriptions
118
Field Descriptions
119
Video Capture Channel X Field 1 Start Register (VCASTRT1, VCBSTRT1)
120
Video Capture Channel X Field 1 Start Register (Vcxstrt1) Field Descriptions
121
Video Capture Channel X Field 1 Stop Register (VCASTOP1, VCBSTOP1)
122
Video Capture Channel X Field 1 Stop Register (Vcxstop1) Field Descriptions
122
Video Capture Channel X Field 2 Start Register (VCASTRT2, VCBSTRT2)
123
Video Capture Channel X Field 2 Start Register (Vcxstrt2) Field Descriptions
123
Video Capture Channel X Field 2 Stop Register (VCASTOP2, VCBSTOP2)
124
Video Capture Channel X Field 2 Stop Register (Vcxstop2) Field Descriptions
124
Video Capture Channel X Vertical Interrupt Register (VCAVINT, VCBVINT)
125
Video Capture Channel X Vertical Interrupt Register (Vcxvint) Field Descriptions
126
Video Capture Channel X Threshold Register (VCATHRLD, VCBTHRLD)
127
Video Capture Channel X Threshold Register (VCATHRLD, VCBTHRLD)
128
Video Capture Channel X Threshold Register (Vcxthrld) Field Descriptions
128
Video Capture Channel X Event Count Register (VCAEVTCT, VCBEVTCT)
129
Video Capture Channel X Event Count Register (Vcxevtct) Field Descriptions
129
Video Capture Channel B Control Register (VCBCTL)
130
Video Capture Channel B Control Register (VCBCTL) Field Descriptions
130
Field Descriptions
130
TSI Capture Control Register (TSICTL)
134
TSI Capture Control Register (TSICTL) Field Descriptions
135
TSI Clock Initialization LSB Register (TSICLKINITL)
136
TSI Clock Initialization LSB Register (TSICLKINITL) Field Descriptions
136
TSI Clock Initialization MSB Register (TSICLKINITM)
137
TSI Clock Initialization MSB Register (TSICLKINITM) Field Descriptions
137
TSI System Time Clock LSB Register (TSISTCLKL)
138
TSI System Time Clock LSB Register (TSISTCLKL) Field Descriptions
138
TSI System Time Clock MSB Register (TSISTCLKM)
139
TSI System Time Clock MSB Register (TSISTCLKM) Field Descriptions
139
TSI System Time Clock Compare LSB Register (TSISTCMPL)
140
TSI System Time Clock Compare LSB Register (TSISTCMPL) Field Descriptions
140
TSI System Time Clock Compare MSB Register (TSISTCMPM)
141
TSI System Time Clock Compare MSB Register (TSISTCMPM) Field Descriptions
141
TSI System Time Clock Compare Mask LSB Register (TSISTMSKL)
142
TSI System Time Clock Compare Mask MSB Register (TSISTMSKM)
143
TSI System Time Clock Ticks Interrupt Register (TSITICKS)
144
TSI System Time Clock Ticks Interrupt Register (TSITICKS) Field Descriptions
144
Video Capture FIFO Registers
145
Video Capture FIFO Registers Function
145
Video Display Port
146
Chapter 4
147
Video Display Mode Selection
147
Image Timing
147
NTSC Compatible Interlaced Display
148
SMPTE 296M Compatible Progressive Scan Display
148
Interlaced Blanking Intervals and Video Areas
149
Video Display Counters
150
Progressive Blanking Intervals and Video Area
150
Horizontal Blanking and Horizontal Sync Timing
151
Sync Signal Generation
152
Vertical Blanking, Sync and Even/Odd Frame Signal Timing
152
External Sync Operation
153
Port Sync Operation
153
Video Display Module Synchronization Chain
153
BT.656 Video Display Mode
154
BT.656 Horizontal Blanking Timing
154
BT.656 Output Sequence
154
Display Timing Reference Codes
154
BT.656 Frame Timing
155
BT.656 Horizontal Blanking Timing
155
Digital Vertical F and V Transitions
156
Blanking Codes
157
BT.656 Image Display
157
BT.656 FIFO Unpacking
158
Bit BT.656 FIFO Unpacking
158
Bit BT.656 FIFO Unpacking
159
BT.656 Dense FIFO Unpacking
160
Y/C Video Display Mode
161
Y/C Display Timing Reference Codes
161
Y/C Horizontal Blanking Timing (BT.1120 60I)
161
Y/C Blanking Codes
162
Y/C Image Display
162
Y/C FIFO Unpacking
162
Bit Y/C FIFO Unpacking
163
Bit Y/C FIFO Unpacking
164
Bit Y/C Dense FIFO Unpacking
165
Video Output Filtering
166
Display Operation
166
Chrominance Resampling Operation
167
Scaling Operation
167
Output Filter Mode Selection
166
Output Filter Modes
166
Edge Pixel Replication
168
Output Edge Pixel Replication
168
X Co-Sited Scaling
168
X Interspersed Scaling
168
Interspersed Chroma Edge Replication
169
Ancillary Data Display
170
Luma Edge Replication
169
Horizontal Ancillary (HANC) Data Display
170
Raw Data Display Mode
170
Raw Mode RGB Output Support
171
Raw Data FIFO Unpacking
171
Vertical Ancillary (VANC) Data Display
170
Bit Raw FIFO Unpacking
171
Bit Raw Dense FIFO Unpacking
172
Bit Raw FIFO Unpacking
172
Bit Raw FIFO Unpacking
173
Bit Raw 3/4 FIFO Unpacking
174
Video Display Field and Frame Operation
175
Display Determination and Notification
175
Video Display Event Generation
177
Display Line Boundary Conditions
178
Display Line Boundary Example
179
Display Timing Examples
180
Interlaced BT.656 Timing Example
180
BT.656 Interlaced Display Horizontal Timing Example
181
BT.656 Interlaced Display Vertical Timing Example
183
Interlaced Raw Display Example
184
Raw Interlaced Display Horizontal Timing Example
185
Raw Interlaced Display Vertical Timing Example
187
Y/C Progressive Display Example
188
Y/C Progressive Display Horizontal Timing Example
189
Y/C Progressive Display Vertical Timing Example
191
Displaying Video in BT.656 or Y/C Mode
192
Displaying Video in Raw Data Mode
194
Handling Underrun Condition of the Display FIFO
196
Video Display Control Registers
197
Video Display Registers
197
Video Display Status Register (VDSTAT)
197
Video Display Control Register (VDCTL)
197
Video Display Frame Size Register (VDFRMSZ)
197
Video Display Horizontal Blanking Register (VDHBLNK)
197
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
197
Video Display Status Register (VDSTAT)
198
Video Display Status Register (VDSTAT) Field Descriptions
199
Video Display Control Register (VDCTL)
200
Video Display Control Register (VDCTL) Field Descriptions
200
Video Display Frame Size Register (VDFRMSZ)
205
Video Display Frame Size Register (VDFRMSZ) Field Descriptions
205
Video Display Horizontal Blanking Register (VDHBLNK)
206
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
207
Video Display Horizontal Blanking Register (VDHBLNK) Field Descriptions
207
Video Display Field 1 Vertical Blanking Start Register (VDVBLKS1)
208
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
209
Video Display Field 1 Vertical Blanking End Register (VDVBLKE1)
210
Video Display Field 2 Vertical Blanking Start Register (VDVBLKS2)
211
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
212
Video Display Field 1 Image Offset Register (VDIMGOFF1)
213
Video Display Field 2 Vertical Blanking End Register (VDVBLKE2)
213
Video Display Field 1 Image Offset Register (VDIMGOFF1)
214
Video Display Field 1 Image Offset Register (VDIMGOFF1) Field Descriptions
214
Video Display Field 1 Image Size Register (VDIMGSZ1)
215
Video Display Field 1 Image Size Register (VDIMGSZ1) Field Descriptions
215
Video Display Field 2 Image Offset Register (VDIMGOFF2)
216
Video Display Field 2 Image Offset Register (VDIMGOFF2) Field Descriptions
217
Video Display Field 2 Image Size Register (VDIMGSZ2)
218
Video Display Field 2 Image Size Register (VDIMGSZ2) Field Descriptions
218
Video Display Field 1 Timing Register (VDFLDT1)
219
Video Display Field 1 Timing Register (VDFLDT1) Field Descriptions
219
Video Display Field 2 Timing Register (VDFLDT2)
220
Video Display Field 2 Timing Register (VDFLDT2) Field Descriptions
220
Video Display Threshold Register (VDTHRLD)
221
Video Display Threshold Register (VDTHRLD) Field Descriptions
222
Video Display Horizontal Synchronization Register (VDHSYNC)
223
Video Display Horizontal Synchronization Register (VDHSYNC) Field Descriptions
223
Video Display Field 1 Vertical Synchronization Start Register (VDVSYNS1)
224
Video Display Field 1 Vertical Synchronization End Register (VDVSYNE1)
225
Video Display Field 2 Vertical Synchronization Start Register (VDVSYNS2)
226
Video Display Field 2 Vertical Synchronization End Register (VDVSYNE2)
227
Video Display Counter Reload Register (VDRELOAD)
228
Video Display Counter Reload Register (VDRELOAD) Field Descriptions
228
Video Display Display Event Register (VDDISPEVT)
229
Video Display Display Event Register (VDDISPEVT) Field Descriptions
229
Video Display Clipping Register (VDCLIP)
230
Video Display Clipping Register (VDCLIP) Field Descriptions
230
Video Display Default Display Value Register (VDDEFVAL)
231
Video Display Default Display Value Register (VDDEFVAL) Field Descriptions
232
Video Display Default Display Value Register (VDDEFVAL)-Raw Data Mode
232
Video Display Vertical Interrupt Register (VDVINT)
233
Video Display Vertical Interrupt Register (VDVINT) Field Descriptions
233
Video Display Field Bit Register (VDFBIT)
234
Video Display Field Bit Register (VDFBIT) Field Descriptions
234
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1)
235
Field Descriptions
236
Video Display Field 1 Vertical Blanking Bit Register (VDVBIT1) Field Descriptions
236
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2)
237
Field Descriptions
238
Video Display Field 2 Vertical Blanking Bit Register (VDVBIT2) Field Descriptions
238
Video Display Register Recommended Values
239
Video Display Registers Recommended Values
239
Video Display FIFO Registers
241
Video Display FIFO Registers Function
241
General Purpose I/O Operation
242
GPIO Registers
243
Video Port Registers
243
Video Port Peripheral Identification Register (VPPID)
244
Video Port Peripheral Identification Register (VPPID) Field Descriptions
244
Video Port Peripheral Control Register (PCR)
245
Video Port Peripheral Control Register (PCR) Field Descriptions
246
Video Port Pin Function Register (PFUNC)
247
Video Port Pin Function Register (PFUNC) Field Descriptions
247
Video Port Pin Direction Register (PDIR)
249
Video Port Pin Direction Register (PDIR) Field Descriptions
249
Video Port Pin Data Input Register (PDIN)
252
Video Port Pin Data Input Register (PDIN) Field Descriptions
253
Video Port Pin Data Output Register (PDOUT)
254
Video Port Pin Data out Register (PDOUT) Field Descriptions
255
Video Port Pin Data Set Register (PDSET)
256
Video Port Pin Data Set Register (PDSET) Field Descriptions
257
Video Port Pin Data Clear Register (PDCLR)
258
Video Port Pin Data Clear Register (PDCLR) Field Descriptions
259
Video Port Pin Interrupt Enable Register (PIEN)
260
Video Port Pin Interrupt Enable Register (PIEN) Field Descriptions
261
Video Port Pin Interrupt Polarity Register (PIPOL)
262
Video Port Pin Interrupt Polarity Register (PIPOL) Field Descriptions
263
Video Port Pin Interrupt Status Register (PISTAT)
264
Video Port Pin Interrupt Status Register (PISTAT) Field Descriptions
265
Video Port Pin Interrupt Clear Register (PICLR)
266
Video Port Pin Interrupt Clear Register (PICLR) Field Descriptions
267
VCXO Interpolated Control Port
268
Chapter 6
269
Overview
269
TSI System Block Diagram
269
Interface
270
Operational Details
270
Program Clock Reference (PCR) Header Format
270
VIC Port Interface Signals
270
Example Values for Interpolation Rate
271
Enabling VIC Port
272
VIC Port Registers
272
VIC Control Register (VICCTL)
273
VIC Control Register (VICCTL) Field Descriptions
273
VIC Port Registers
274
VIC Input Register (VICIN)
275
VIC Input Register (VICIN) Field Descriptions
275
VIC Clock Divider Register (VICDIV)
276
VIC Clock Divider Register (VICDIV) Field Descriptions
276
Video Port Configuration Examples
277
Example 1: Noncontinuous Frame Capture for 525/60 Format
278
Examples in this Appendix Use the Video Port Chip Support Library (CSL).
278
Example 2: Noncontinuous Frame Display for 525/60 Format
286
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Texas Instruments TMS320C64x DSP Programmer's Reference Manual (169 pages)
DSP Little-Endian DSP Library
Brand:
Texas Instruments
| Category:
Software
| Size: 0.32 MB
Table of Contents
Read this First
3
Table of Contents
5
1 Introduction
9
Introduction to the TI C64X+ DSPLIB
10
Features and Benefits
12
2 Installing and Using DSPLIB
13
How to Install DSPLIB
14
Using DSPLIB
15
DSPLIB Arguments and Data Types
15
DSPLIB Data Types
15
Calling a DSPLIB Function from C
16
Calling a DSP Function from Assembly
16
DSPLIB Testing − Allowable Error
16
DSPLIB Overflow and Scaling Issues
16
Interrupt Behavior of DSPLIB Functions
17
How to Rebuild DSPLIB
17
3 DSPLIB Function Tables
19
Arguments and Conventions Used
20
Argument Conventions
20
4 DSPLIB Reference
21
DSPLIB Functions
21
DSPLIB Function Tables
21
Adaptive Filtering
21
Adaptive Filtering
22
Correlation
22
Filtering and Convolution
23
Math
24
Matrix
24
Miscellaneous
25
Functions Optimized in the C64X+ DSPLIB
26
Correlation
29
Fft
29
Filtering and Convolution
29
Math
29
Miscellaneous
29
Obsolete Functions
29
Adaptive Filtering
30
Correlation
32
Fft
36
Filtering and Convolution
66
Math
86
Matrix
101
Miscellaneous
104
Obsolete Functions
118
A.1 Performance Considerations
150
A.2 Fractional Q Formats
151
A.2.1 Q3.12 Format
151
A.2.2 Q.15 Format
151
Q3.12 Bit Fields
151
A−2 Q.15 Bit Fields
151
A.2.3 Q.31 Format
152
A−3 Q.31 Low Memory Location Bit Fields
152
A−4 Q.31 High Memory Location Bit Fields
152
B.1 DSPLIB Software Updates
153
B.2 DSPLIB Customer Support
153
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