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TMS320C6201 Silicon Errata
Workaround:
Advisory 2.1.4
Revision(s) Affected:
Workaround:
Advisory 2.1.5
Revision(s) Affected:
Details:
Workaround:
Avoid use of multiple CE spaces of SDRAM within a single refresh period.
DMA: RSYNC Cleared Late for Frame-synchronized Transfer
2.1 and 2.0
In a frame-synchronized transfer, RSYNC is only cleared after the beginning of last write
transfer. It should occur after the start of the first read transfer in the synchronized frame.
(Internal reference number 0267)
Wait until end-of-frame (perhaps using DMAC pins for external status) to issue next frame
synchronization.
2.1 and 2.0
If any element size other than 32 bits is written to the DXR of either serial port, then the
register is not copied to the XSR. (Internal reference number 0511)
The following workaround is applicable only for non-split mode DMA transfers.
1. For little-endian mode:
Always write 32 bits to the DXR. When using the DMA, it is possible to perform word transfers,
but increment or decrement the address by one or two bytes using one of the global index
registers. If the serial port is transferring out 16-bit words, which are stored on consecutive
half-word boundaries in memory (either internal or external), the DMA would need to be set up
such that it performs word writes to DXR (ESIZE = 00b). The global index register used would
need an element index of 0x0002 (2 bytes). If an 8-bit data transfer is desired, then element
index would need to be 0x0001.
Please note that this workaround assumes that the receive justification, RJUST in the
McBSP's SPCR is set for right justification (zero-fill or sign-extended). If left justification is
chosen for receive data, the DMA receive src address pointing to DRR should be changed to
DRR+3 (which is 0x018C0003 for McBSP0 and 0x01900003 for McBSP1) for byte-size
elements and DRR+2 for half-word elements. This ensures packing data on byte or half-word
boundaries for receive data.
EMIF: SDRAM Invalid Access (Continued)
McBSP: DXR to XSR Copy Not Generated
SPRZ153
16
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