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signal groups description
CLKIN
CLKOUT2
CLKOUT1
CLKMODE1
CLKMODE0
PLLFREQ3
PLLFREQ2
PLLFREQ1
PLLV
PLLG
PLLF
TMS
TDO
TDI
TCK
TRST
EMU1
EMU0
RSV9
RSV8
RSV7
RSV6
RSV5
RSV4
RSV3
RSV2
RSV1
RSV0
HD[15:0]
HCNTL0
HCNTL1
HHWIL
HBE1
HBE0
Clock/PLL
JTAG
Emulation
Reserved
Control/Status
16
Data
Register Select
Half-Word/Byte
Select
Figure 2. CPU (DSP Core) and Peripheral Signals
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
Boot Mode
Reset and
Interrupts
Little ENDIAN
Big ENDIAN
DMA Status
Power-Down
Status
HPI
(Host-Port Interface)
Control
•
HOUSTON, TEXAS 77251--1443
TMS320C6201
BOOTMODE4
BOOTMODE3
BOOTMODE2
BOOTMODE1
BOOTMODE0
RESET
NMI
EXT_INT7
EXT_INT6
EXT_INT5
EXT_INT4
IACK
INUM3
INUM2
INUM1
INUM0
LENDIAN
DMAC3
DMAC2
DMAC1
DMAC0
PD
HAS
HR/W
HCS
HDS1
HDS2
HRDY
HINT
7
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