Table of Contents
Advertisement
TMS320C6201 Silicon Errata
Advisory 2.1.7
Revision(s) Affected:
Details:
Workaround:
Advisory 2.1.8
Revision(s) Affected:
Details:
Workaround:
Advisory 2.1.9
Revision(s) Affected:
Details:
Workaround:
Advisory 2.1.10
Revision(s) Affected:
Details:
Workaround:
2.1 and 2.0
If DMA Channel 0 is configured to perform a multiframe split-mode transfer, it is possible for
the last element of the last frame of the Receive Read to not be transferred. After the last
element of the last frame of the Transmit Write Transfer, the element count is reloaded into the
Channel 0 Transfer Counter Register, which may allow for the Transmit Read Transfer to be
initiated. If the read synchronization and write synchronization are far enough apart in CPU
cycles, then it is possible for the DMA to hang (due to the Transmit Read) before the Receive
Write gets its sync event and completes the transmission. (Internal reference number 0558)
If a multiframe split-mode transfer is required, use DMA channel 1, 2, or 3.
2.1 and 2.0
When FUNC = 1 (TOUT is a timer pin), if CLKSRC = 0 (external clock source), the TOUT pin
is not driven with TSTAT. The timer still functions correctly, but the output is not seen
externally. (Internal reference number 0568)
None. Timer functions correctly.
2.1 and 2.0
The power-down pin, PD, only goes high (active) in power-down mode 3, not in power-down
mode 2. (Internal reference number 0537)
None. Power-down modes function correctly.
2.1 and 2.0
If RBTR8=1, a requester with continuous requests will not relinquish control of the EMIF even
to a higher-priority requester. (Internal reference number 0432)
Leave RBTR8 set to the default of 0.
DMA Channel 0 Multiframe Split-Mode Incompletion
Timer Clock Output Not Driven for External Clock
Power-Down Pin PD Not Set High for Power-Down 2 Mode
EMIF: RBTR8 Bit Not Functional
SPRZ153
19
Advertisement
Table of Contents
