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PRWD FIELD
POWER-DOWN
(BITS 15- -10)
MODE
000000
No power-down
001001
PD1
010001
PD1
†
011010
PD2
†
011100
PD3
All others
Reserved
†
When entering PD2 and PD3, all functional I/O remains in the previous state. However, for peripherals which are asynchronous in nature or
peripherals with an external clock source, output signals may transition in response to stimulus on the inputs. Under these conditions,
peripherals will not operate according to specifications.
power-supply sequencing
TI DSPs do not require specific power sequencing between the core supply and the I/O supply. However,
systems should be designed to ensure that neither supply is powered up for extended periods of time if the other
supply is below the proper operating voltage.
system-level design considerations
System-level design considerations, such as bus contention, may require supply sequencing to be
implemented. In this case, the core supply should be powered up at the same time as, or prior to (and powered
down after), the I/O buffers. This is to ensure that the I/O buffers receive valid inputs from the core before the
output buffers are powered up, thus, preventing bus contention with other chips on the board.
power-supply design considerations
For systems using the C6000 DSP platform of devices, the core supply may be required to provide in excess
of 2 A per DSP until the I/O supply is powered up. This extra current condition is a result of uninitialized logic
within the DSP(s) and is corrected once the CPU sees an internal clock pulse. With the PLL enabled, as the
I/O supply is powered on, a clock pulse is produced stopping the extra current draw from the supply. With the
PLL disabled, an external clock pulse may be required to stop this extra current draw. A normal current state
returns once the I/O power supply is turned on and the CPU sees a clock pulse. Decreasing the amount of time
between the core supply power up and the I/O supply power up can minimize the effects of this current draw.
A dual-power supply with simultaneous sequencing, such as available with TPS563xx controllers or PT69xx
plug-in power modules, can be used to eliminate the delay between core and I/O power up [see the Using the
TPS56300 to Power DSPs Application Report (literature number SLVA088)]. A Schottky diode can also be used
to tie the core rail to the I/O rail, effectively pulling up the I/O power supply to a level that can help initialize the
logic within the DSP.
Table 3. Characteristics of the Power-Down Modes
WAKE-UP METHOD
—
Wake by an enabled interrupt
Wake by an enabled or
non-enabled interrupt
Wake by a device reset
Wake by a device reset
—
•
POST OFFICE BOX 1443
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004
EFFECT ON CHIP'S OPERATION
CPU halted (except for the interrupt logic)
Power-down mode blocks the internal clock inputs at the
Power down mode blocks the internal clock inputs at the
boundary of the CPU, preventing most of the CPU's logic from
switching. During PD1, DMA transactions can proceed between
peripherals and internal memory.
Output clock from PLL is halted, stopping the internal clock
structure from switching and resulting in the entire chip being
halted. All register and internal RAM contents are preserved. All
functional I/O "freeze" in the last state when the PLL clock is
turned off.
Input clock to the PLL stops generating clocks. All register and
internal RAM contents are preserved. All functional I/O "freeze" in
the last state when the PLL clock is turned off. Following reset, the
PLL needs time to re-lock, just as it does following power-up.
Wake-up from PD3 takes longer than wake-up from PD2 because
the PLL needs to be re-locked.
HOUSTON, TEXAS 77251--1443
TMS320C6201
—
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