Clock Pll - Texas Instruments TMS320C6201 Manual

TMS320C6201
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS051H -- JANUARY 1997 -- REVISED MARCH 2004

clock PLL

All of the C62x clocks are generated from a single source through the CLKIN pin. This source clock either drives
the PLL, which generates the internal CPU clock, or bypasses the PLL to become the CPU clock.
To use the PLL to generate the CPU clock, the filter circuit shown in Figure 5 must be properly designed. Note
that for C6201, the EMI filter must be powered by the I/O voltage (3.3 V).
To configure the C62x PLL clock for proper operation, see Figure 5 and Table 2. To minimize the clock jitter, a
single clean power supply should power both the C62x DSP device and the external clock oscillator circuit. The
minimum CLKIN rise and fall times should also be observed. See the input and output clocks section for input
clock timing requirements.
3.3 V 3 OUT
C3 C4
10 μF 0.1 μF
1 IN
2
(Bypass)
GND
NOTES: A. Keep the lead length and the number of vias between pin PLLF, pin PLLG, R1, C1, and C2 to a minimum. In addition, place all PLL
components (R1, C1, C2, C3, C4, and EMI Filter) as close to the C6000
with the PLL components on a single side of the board without jumpers, switches, or components other than the ones shown. For
CLKMODE x4, values for C1, C2, and R1 are fixed and apply to all valid frequency ranges of CLKIN and CLKOUT.
B. For CLKMODE x1, the PLL is bypassed and all six external PLL components can be removed. For this case, the PLLV terminal has
to be connected to a clean supply and the PLLG and PLLF terminals should be tied together.
C. Due to overlap of frequency ranges when choosing the PLLFREQ, more than one frequency range can contain the CLKOUT1
frequency. Choose the lowest frequency range that includes the desired frequency. For example, for CLKOUT1 = 133 MHz, a
PLLFREQ value of 000b should be used. For CLKOUT1 = 200 MHz, PLLFREQ should be set to 001b. PLLFREQ values other than
000b, 001b, and 010b are reserved.
D. The 3.3-V supply for the EMI filter (and PLLV) must be from the same 3.3-V power plane supplying the I/O voltage, DV
E. EMI filter manufacturer TDK part number ACF451832-153-T
24
0 1 0
0 0 1
0 0 0
PLLV
PLLF
R1
PLLG
C1 C2
CLKIN
1 1
0 1
1 0
0 0
Figure 5. PLL Block Diagram
•
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
CLKOUT1 Frequency Range 130- -233 MHz
CLKOUT1 Frequency Range 65- -200 MHz
CLKOUT1 Frequency Range 50- -140 MHz
C6201
CLKOUT
- - MULT×4 f(CLKOUT)=f(CLKIN)×4
- - Reserved
- - Reserved
- - MULT×1 f(CLKOUT)=f(CLKIN)
™
DSP device as possible. Best performance is achieved
EMIF
CLKOUT1
CLKOUT2
SSCLK
SDCLK
.
DD