Memory Map; Figure C-1: Pma Attribute Bus Waveform; Appendix C: Pma Attribute Programming Bus; Table C-2: Pma Attribute Memory Map - Xilinx RocketIO X User Manual

R
Register access is via a simple, active-low strobe cycle. A write cycle followed by a read
cycle is illustrated in Figure C-1. When PMAREGSTROBE is unasserted (High), both read
and write access are inhibited. PMAREGADDR[5], PMAREGRW, and
PMAREGDATAIN[7:0] must be stable during PMAREGSTROBE asserted (Low) and also
meet setup and hold timing relative to the falling and rising edges of PMAREGSTROBE,
respectively.

Memory Map

The PMA registers are byte-wide (8-bit) and memory mapped, based on
PMAREGADDR[5:0]. The memory assignment and register layout are shown in
Reserved bits are shown in grey and should be set to 0. Reserved registers are also shown
in grey and should not be written.

Table C-2: PMA Attribute Memory Map

Address Register Name
0x00 MASTERBIAS
0x01 TXDIVRATIOLO
0x02 TXDIVRATIOHI
0x03 TXLOOPFILTER
0x04 TXMODECONTROL
0x05 TXOUTPUTLEVEL
0x06 TXOUTPUTMODE
0x07 RXDIVRATIOLO
0x08 RXDIVRATIOHI
0x09 RXLOOPFILTER
0x0A RXMODE0
148
PMAREGADDR[]
PMAREGRW
PMAREGDATAIN[]
PMAREGSTROBE
TXRUNDISP

Figure C-1: PMA Attribute Bus Waveform

7 6
SEL_DAC_FIX[3:2]
IBOOST
TXREG[1:0]
SLEW EMPOFF
TXANASW
SEL_DAC_TRAN[1:0]
SEL_DAC_FIX[1:0] AFE_FLAT_
ENABLE
RXREG[1:0]
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Appendix C: PMA Attribute Programming Bus

ADDR[]
DATAIN[]
t SU
t H
5 4 3
VCODAC[5:0]
TXDIVRATIO[7:0]
SEL_DAC_TRAN[3:2] ENDCD
TXLOOPFILTERR[1:0]
TXVSEL[1:0] TXVCOGAIN
PRDRVOFF
TXDIGSW
RXDIVRATIO[7:0]
RXDIVRATIO[13:8]
RXLOOPFILTERR[2:0]
RXVSEL[1:0] RXVCOGAIN RXVCODAC
ADDR[]
t SU t H
t CO
t CX
DATAOUT[]
ug035_C-1_021204
Table
2 1
MASTERBIAS[1:0]
TXBUSWID TXDIVRATIO[9:8]
TXLOOPFILTERC[1:0]
TXVCODAC
TXDOWNLEVEL[3:0]
TXEMPHLEVEL[3:0]
RXLOOPFILTERC[1:0]
RXCPI
RocketIO™ X Transceiver User Guide
UG035 (v1.5) November 22, 2004
C-2.
0
TXCPI
RXVCOSW