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Implementation variables generally fit one of three trade-off patterns: more or less of
a feature; inclusion or exclusion of a feature; hardware implementation or software
emulation of a feature. An example of each trade-off follows:
•
More or less of a feature—For example, to fine-tune performance, you can
increase or decrease the amount of instruction cache memory. A larger cache
increases execution speed of large programs, while a smaller cache conserves on-
chip memory resources.
•
Inclusion or exclusion of a feature—For example, to reduce cost, you can choose
to omit the JTAG debug module. This decision conserves on-chip logic and
memory resources, but it eliminates the ability to use a software debugger to
debug applications.
•
Hardware implementation or software emulation—For example, in control
applications that rarely perform complex arithmetic, you can choose for the
division instruction to be emulated in software. Removing the divide hardware
conserves on-chip resources but increases the execution time of division
operations.
For information about which Nios II cores supports what features, refer to the Nios II
Core Implementation Details chapter of the Nios II Processor Reference Handbook.
For complete details about user-selectable parameters for the Nios II processor, refer
to the Instantiating the Nios II Processor chapter of the Nios II Processor Reference
Handbook.
Related Information
•
Instantiating the Nios II Processor
•
Nios II Core Implementation Details
•
Instruction Set Reference
2.2. Register File
The Nios II architecture supports a flat register file, consisting of thirty-two 32-bit
general-purpose integer registers, and up to thirty-two 32-bit control registers. The
architecture supports supervisor and user modes that allow system code to protect the
control registers from errant applications.
The Nios II processor can optionally have one or more shadow register sets. A shadow
register set is a complete set of Nios II general-purpose registers. When shadow
register sets are implemented, the
register set is currently in use. An instruction access to a general-purpose register
uses whichever register set is active.
A typical use of shadow register sets is to accelerate context switching. When shadow
register sets are implemented, the Nios II processor has two special instructions,
and
rdprs
typically manipulated by an operating system kernel, and are transparent to
application code. A Nios II processor can have up to 63 shadow register sets.
The Nios II architecture allows for the future addition of floating-point registers.
For details about shadow register set implementation and usage, refer to "Registers"
and "Exception Processing" in the Programming Model chapter of the Nios II Processor
Reference Handbook.
Nios II Processor Reference Guide
16
on page 169
, for moving data between register sets. Shadow register sets are
wrprs
on page 106
on page 121
field of the
CRS
status
2. Processor Architecture
NII-PRG | 2018.04.18
register indicates which
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