Skpd-Scratchpad Data Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
31:20
19:1
0
2.5.32 SKPD—Scratchpad Data Register
This register holds 32 writable bits with no functionality behind them. It is for the
convenience of BIOS and graphics drivers.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
Bit
31:0
Datasheet, Volume 2
0/0/0/PCI
BC–BFh
00100000h
RW-KL, RW-L
32 bits
00000h
Reset RST/
Attr
Value PWR
RW-L 001h Uncore
RO 0h
RW-KL 0b Uncore
0/0/0/PCI
DC–DFh
00000000h
RW
32 bits
Reset RST/
Attr
Value PWR
RW 00000000h Uncore
Description
Top of Low Usable DRAM (TOLUD)
This register contains bits 31:20 of an address one byte above the
maximum DRAM memory below 4 GB that is usable by the
operating system. Address bits 31:20 programmed to 01h implies
a minimum memory size of 1 MB. Configuration software must set
this value to the smaller of the following 2 choices: maximum
amount memory in the system minus ME stolen memory plus one
byte or the minimum address allocated for PCI memory. Address
bits 19:0 are assumed to be 0_0000h for the purposes of address
comparison. The Host interface positively decodes an address
towards DRAM if the incoming address is less than the value
programmed in this register.
The Top of Low Usable DRAM is the lowest address above both
Graphics Stolen memory and TSEG. BIOS determines the base of
Graphics Stolen Memory by subtracting the Graphics Stolen
Memory Size from TOLUD and further decrements by TSEG size to
determine base of TSEG. All the Bits in this register are locked in
Intel TXT mode.
This register must be 1MB aligned when reclaim is enabled.
Reserved
Lock (LOCK)
This bit will lock all writeable settings in this register, including
itself.
Description
Scratchpad Data (SKPD)
1 DWORD of data storage.
79