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Integrated Graphics Display Port
8.1.6.
HSYNC and VSYNC Design Considerations
HSYNC and VSYNC signals are connected to the analog display attached to the VGA connector. These
are 3.3-V outputs from the GMCH. Some monitors have been found to drive HSYNC and VSYNC
signals during reset. Because these signals are used as straps on the 852GM/GME and 855GM/GME
chipsets, the GMCH can enter an illegal state under these conditions. In order to prevent these signals
from being driven to the GMCH during reset, system designers must ensure the GMCH is isolated from
any monitor driving HSYNC or VSYNC while PCI_RST# is active. Appropriate logic is required
between the GMCH and the VGA connector (both the on-board VGA connector and the VGA connector
at the docking station) to accomplish this.
Intel's recommended option is to use an analog switch (i.e. discrete FET, Q-buffer) to switch these
signals between the on-board VGA connector and the docking connector. In this case, footprints for a
series resistor and an optional capacitor are needed on each of these signals to meet the VESA electrical
specifications for video signals. Resistor and capacitor values of 39ohm and 33pF respectively are used
on the CRB. These values were calculated based on the GMCH buffer strength and board routing.
Customers are recommended to perform a signal integrity check specific to their board topology to
determine the appropriate resistor and capacitor values for their platforms.
An alternative option is to use a unidirectional buffer on each of these signals. For each of the HSYNC
and VSYNC signals, a footprint for a series resistor must be placed between the GMCH and the
unidirectional buffer to prevent excessive overshoot and undershoot at the input of the buffer.
Consideration should also be taken in designing the filter circuit on the output of these buffers to ensure
that the VESA electrical specifications for video signals are met at both the on-board VGA connector as
well as on the docking station. Customers are strongly encouraged to perform complete signal integrity
validation at the input of the buffer and at the VGA connectors.
8.1.7.
DDC and I2C Design Considerations
DDCADATA and DDCACLK are 3.3-V IO buffers connecting the GMCH to the monitor. If higher
signaling voltage (5V) is required by the monitor, level shifting devices may be used. Pull-up resistors
of 2.2-kΩ (or of the appropriate value derived from simulation) are required on each of these signals.
8.2.
LVDS Transmitter Interface
The Intel LVDS (Low Voltage Differential Signaling) transmitter serializer converts up to 24 bits of
parallel digital RGB data, (8 bits per RGB), along with up to 4 bits for control (SHFCLK, HSYNC,
VSYNC, DE) into 2, 4 channel serial bit streams, for output by the LVDS transmitter.
The transmitter is fully differential and utilizes a current mode drive with a high impedance output. The
drive current develops a differential swing in the range of 250 mV to 450 mV across a 100-Ω
termination load.
The parallel digital data is serially converted to a 7-bit serial bit stream that is transmitted over the 8
channel LVDS interface at 7x the input clock. The differential output clock channel transmits the output
clock at the input clock frequency. While the differential output channels transmit the data at the 7x
clock rate (1 bit time is 7x the input clock). The 7x serializer will synchronize and regenerate and input
clock from 35 MHz to 112 MHz. Typical operation is at 65 MHz (15.4 ns), therefore, at a 7x clock rate,
1bit time would be 2.2 ns. With data cycle times as small as 2.2 ns, propagation delay mismatch is
critical, such that intra-channel skew (skew between the inverting and non-inverting output) must be
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Intel
855GM/855GME Chipset Platform Design Guide
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