Dvo Interface Signal Groups; Dvo/I2C To Agp Pin Mapping - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Integrated Graphics Display Port
6.3.1

DVO Interface Signal Groups

Table 48
Table 48. DVO Interface Signal Groups
Signal
Group
DVOB
Common
Signals for
Both DVO
Ports
2
6.3.1.1 DVO/I
The DVODETECT signal is muxed with the GPAR signal on the AGP bus. This signal will act as a
strap to indicate if the interface is in AGP or DVO mode. The GMCH has an internal 8.2-k,
pull-down on this signal that will naturally pull it low. If an AGP graphics device is present, the
signal will be pulled high at the AGP graphics device and the AGP/DVO mux select bit in the
SHIC register will be set to AGP mode.
The SBA[7:0] signals act as straps for an ADDID. These pins are used to communicate to the
Video BIOS when an external device is interfaced to the DVO port. If an on-board DVO device is
implemented, ADDID[7] should be strapped low. When an AGP graphics device is present,
DVODETECT=1 (AGP mode).
162
®
6300ESB ICH Embedded Platform Design Guide
shows the DVO interface signal groups.
GMCH Signal
Name
DVOBFLDSTL
DVOBHSYNC
DVOBVSYNC
DVOBBLANK#
DVOBD[11:0]
DVOBCLK
(DVOBCLK[0])
DVOBCLK#
(DVOBCLK[1])
DVOBCCLKINT
DVOBCINTR#
ADDID[7:0]
DVODETECT
C to AGP Pin Mapping
Signal Signal
Type Group
Input DVOCFLDSTL
Output
Output
Output DVOCBLANK#
DVOC
Output
Output
Strobe
(DVOCCLK[0])
Output
Strobe
(DVOCCLK[1])
Input
Voltage
Input
Reference,
Input
RCOMP
Input
GMCH Signal Signal
Name Type
Input
DVOCHSYNC Output
DVOCVSYNC Output
Output
DVOCD[11:0] Output
DVOCCLK
Output
Strobe
DVOCCLK#
Output
Strobe
DVORCOMP
GVREF