Memory Read; Memory Write; Reading And Writing I/O Ports; I/O Read - Intel Quark SoC X1000 User Manual

using linear, two-field virtual, and three-field virtual must first be translated to the
physical address form before being used to read or write memory.
5.7.2

Memory Read

1. Clear CR0.PG bit if is it 1.
2. Write address to EAX.
3. Submit the read instruction to the core: MOV EDX, DWORD PTR [EAX].
4. Read memory data from EDX via the SRAM and PDR.
5. Restore CR0.PG bit if it was changed in the first step.
5.7.3

Memory Write

1. Clear CR0.PG bit if it is 1.
2. Write address to EAX.
3. Write data to EDX.
4. Submit the memory write instruction to the core: MOV DWORD PTR [EAX], EDX.
5. Restore the CR0.PG bit if it was changed in the first step.
5.8

Reading and Writing I/O Ports

The Intel
OUT instructions submitted to the core via the TAP.
Note: The CR0.PG bit must be 0 prior to using the PIR TAP instructions to submit I/O read
and write instructions.
5.8.1

I/O Read

1. Write the I/O address to read from to the DX register.
2. Submit one of the following based on the desired access width:
 1 byte wide read: IN AL, DX
 2 byte wide read: IN AX, DX
 4 byte wide read: IN EAX, DX
5.8.2

I/O Write

1. Write the I/O address for the write to the DX register.
2. Write the data to be written to the EAX register.
3. Submit one of the following based on the desired access width:
 1 byte wide write: OUT DX, AL
 2 byte wide write: OUT DX, AX
 4 byte wide write: OUT DX, EAX
24
®
Quark SoC X1000 Core supports I/O port reads and writes using the IN and
Run Control
Order Number: 329866-002US