Interfaces; System Memory Interface; System Memory Technology Support; System Memory Timing Support - Intel BX80619I73960X Datasheet

Interfaces

2
Interfaces
This chapter describes the functional behaviors supported by the processor.
2.1

System Memory Interface

2.1.1

System Memory Technology Support

The Integrated Memory Controller (IMC) supports DDR3 protocols with four
independent 64-bit memory channels and supports 1 unbuffered DIMM per channel.
2.1.2

System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
2.2

PCI Express* Interface

This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express* Base Specification for details of PCI Express*.
Note: The processor is capable of up to 8.0 GT/s speeds.
2.2.1

PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses
standard mechanisms as defined in the PCI Plug-and-Play specification.
The PCI Express architecture is specified in three layers — Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. Refer to
Datasheet, Volume 1
Figure 2-1 for the PCI Express Layering Diagram.
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