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Table 4.
Supported DIMM Module Configurations (Sheet 2 of 2)
Raw
DIMM
Card
Capacity
Version
Technology
512 MB
D
1 GB
2 GB
1 GB
E
2 GB
4 GB
512 MB
F
1 GB
2 GB
2.1.2
System Memory Timing Support
The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and
command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every
clock. Command launch mode programming depends on the transfer rate and
memory configuration.
Table 5.
DDR3 System Memory Timing Support
Transfer
Rate
(MT/s)
800
1066
NOTES:
1.
System Memory timing support is based on availability and is subject to change.
2.1.3
System Memory Organization Modes
The IMC supports two memory organization modes, single-channel and dual-channel.
Depending upon how the DIMM Modules are populated in each memory channel, a
number of different configurations can exist.
2.1.3.1
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
®
TM
Intel
Core
i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel
Datasheet Addendum
16
DRAM
DRAM
Device
Organization
512 Mb
64 M x 8
1 Gb
128 M x 8
2 Gb
256 M x 8
512 Mb
64M x 8
1 Gb
128 M x 8
2 Gb
256 M x 8
512 Mb
32 M x 16
1 Gb
64 M x 16
2 Gb
128 M x 16
tCL
tRCD
(tCK)
(tCK)
6
7
8
# of
# of Row/
# of
Physical
DRAM
Device
Devices
Ranks
9
1
9
1
9
1
18
2
18
2
18
2
8
2
8
2
8
2
tRP
(tCK)
(tCK)
6
6
7
7
8
8
®
®
Celeron
Processor P4505, U3405 Series
Interfaces
# of
Col
Banks
Address
Inside
Bits
DRAM
13/10
8
14/10
8
15/10
8
13/10
8
14/10
8
15/10
8
12/10
8
13/10
8
14/10
8
CWL
CMD Mode
Notes
5
1n
6
1n
August 2010
Document Number: 323178-003
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Size
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