Sdmatim-Synchronous Dma Timing Register (Function 1) - Intel 460GX Software Developer’s Manual

IDE Configuration
12.2.13 SDMATIM–Synchronous DMA Timing Register (Function 1)
Address Offset:
Default Value:
Attribute:
This register controls the timings used by each Synchronous DMA enabled device. For non-
synchronous DMA operation, this register should be left programmed to its default value.
Bit
15:14
13:12
11:10
9:8
7:6
5:4
3:2
1:0
12-8
4A-4Bh
0000h
Read/Write only
Reserved.
Secondary Drive 1 Cycle Time (SCT1): These bit settings determine the minimum data write
strobe Cycle Time (CT) and minimum Ready to Pause time (RP).
00: CT = 4 PCICLK, RP = 6 PCICLK
01: CT = 3 PCICLK, RP = 5 PCICLK
10: CT = 2 PCICLK, RP = 4 PCICLK
11: Reserved
Reserved.
Secondary Drive 0 Cycle Time (SCT0): These bit settings determine the minimum data write
strobe Cycle Time (CT) and minimum Ready to Pause time (RP).
00: CT = 4 PCICLK, RP = 6 PCICLK
01: CT = 3 PCICLK, RP = 5 PCICLK
10: CT = 2 PCICLK, RP = 4 PCICLK
11: Reserved
Reserved.
Primary Drive 1 Cycle Time (PCT1): These bit settings determine the minimum data write
strobe Cycle Time (CT) and minimum Ready to Pause time (RP).
00: CT = 4 PCICLK, RP = 6 PCICLK
01: CT = 3 PCICLK, RP = 5 PCICLK
10: CT = 2 PCICLK, RP = 4 PCICLK
11: Reserved
Reserved.
Primary Drive 0 Cycle Time (PCT0): These bit settings determine the minimum data write
strobe Cycle Time (CT) and minimum Ready to Pause time (RP).
00: CT = 4 PCICLK, RP = 6 PCICLK
01: CT = 3 PCICLK, RP = 5 PCICLK
10: CT = 2 PCICLK, RP = 4 PCICLK
11: Reserved
Description
Intel® 460GX Chipset Software Developer's Manual