Inter-Integrated Circuit (I2C) Interface; I2C Timing Diagram - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 13 Inter-integrated Circuit (I2C) interface
The Internal Integrated Circuit Bus (I2C) is widely used for communication between microcontrollers and
sensors and other off-chip modules, it supports multi-master and multi-slave modes, and can communicate at
100KHz (standard) and 400KHz (fast) using only two lines (SDA and SCL). Timing and DMA, with CRC
checksum function.
13.1 Main features
l Support master and slave modes
l Support 7-bit or 10-bit addresses
l Slave devices support dual 7-bit addresses
l Support two speed modes: 100KHz and 400KHz
l Multiple status modes, multiple error flags
l Support extended clock function
l 2 interrupt vectors
l
DMA support
l Support PEC
l SMBus compatible
13.2 Overview
I2C is a half-duplex bus that can only operate in one of the following four modes at the same time: master
device transmit mode, master device receive mode, slave device transmit mode and slave device receive mode.
the I2C module works in slave mode by default and automatically switches to master mode when a start
condition is generated and to slave mode when arbitration is lost or a stop signal is generated. the I2C module
supports multi-master functionality. When working in master mode, the I2C module actively emits data and
addresses. Both data and address are transmitted in 8-bit units, with the high bit before and the low bit after.
After the start event is a one-byte (in 7-bit address mode) or two-byte (in 10-bit address mode) address, and
for every 8-bit data or address sent by the host, the slave needs to reply with an answer ACK, which pulls the
SDA bus low, as shown in Figure 13-1.
In order to work properly the I2C must be fed with the correct clock, which is a minimum of 2MHz in standard
mode and 4MHz in fast mode.
V1.3
Figure 13-1 I2C Timing Diagram
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