WCH CH32V003 Series Reference Manual page 103

CH32V003 Reference Manual
Reserved
Bit Name
[15:8] Reserved
7 BG
6 TG
5 COMG
4 CC4G
3 CC3G
2 CC2G
1 CC1G
0 UG
V1.3
BG
Access
RO Reserved
The brake event generation bit, which is set and cleared
by software, is used to generate a brake event.
1: Generate a brake event. At this point, MOE=0,
WO BIF=1, if the corresponding interrupt and DMA are
enabled, the corresponding interrupt and DMA are
generated.
0: No action.
The trigger event generation bit, which is set by
software and cleared by hardware, is used to generate a
trigger event.
WO 1: Generate a trigger event, TIF is set, and the
corresponding interrupts and DMAs are generated if
enabled.
0: No action.
Compare capture control update generation bit.
Generates a compare capture control update event. This
bit is set by software and automatically cleared by
hardware.
WO 1: when CCPC = 1, allow updating of CCxE, CCxNE,
OCxM bits.
0: No action.
Note: This bit is only valid for channels with
complementary outputs (channels 1, 2, 3).
Compare capture event generation bit 4. generates
WO
compare capture event 4.
Compare capture event generation bit 3. generates
WO
compare capture event 3.
Compare capture event generation bit 2. generates
WO
compare capture event 2.
Compare capture event generation bit 1. generates
compare capture event 1.
This bit is set by software and cleared by hardware. It
is used to generate a compare capture event.
1: Generate a compare capture event on compare
capture channel 1.
If compare capture channel 1 is configured as
output.
WO
Set the CC1IF bit. Generate the corresponding
interrupts and DMAs if they are enabled.
If compare capture channel 1 is configured as input.
The current core counter value is captured to compare
capture register 1; set the CC1IF bit to generate the
corresponding interrupts and DMAs if they are enabled;
if CC1IF is already set, set the CC1OF bit.
0: No action.
Update event generation bit to generate an update
event. This bit is set by software and is automatically
cleared by hardware.
1: Initialize the counter and generate an update event.
WO
0: No action.
Note: The prescaler counter is also cleared to zero, but
the prescaler factor remains unchanged. The core
counter is cleared if in centrosymmetric mode or
103
TG COMG CC4G CC3G CC2G CC1G UG
Description
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Reset
value
0
0
0
0
0
0
0
0
0