Clock Configuration Register0 (Rcc_Cfgr0) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

3.4.2 Clock configuration register0 (RCC_CFGR0)

Offset address: 0x04
31 30 29 28
Reserved
15 14 13 12
ADCPRE[4:0]
Bit Name
[31:27] Reserved
[26:24] MCO
[23:17] Reserved
16 PLLSRC
[15:11] ADCPRE
[10:8] Reserved
[7:4] HPRE
V1.3
27 26 25 24
MCO[2:0]
11 10 9 8
Reserved
Access
RO Reserved
Microcontroller MCO pin clock output control.
0xx: no clock output.
100: System clock (SYSCLK) output.
RW 101: Internal 24 MHz RC oscillator clock
(HSI) output.
110: External oscillator clock (HSE) output.
111: PLL clock output.
RO Reserved
Input clock source for PLL (write only when PLL is off).
RW 1: HSE is fed into PLL without dividing the frequency.
0: HSI is not divided and sent to PLL.
ADC clock source prescaler control {13:11,15:14}.
000xx: AHBCLK divided by 2 as ADC clock.
010xx: AHBCLK divided by 4 as ADC clock.
100xx: AHBCLK divided by 6 as ADC clock.
110xx: AHBCLK divided by 8 as ADC clock.
00100: AHBCLK divided by 4 as ADC clock.
01100: AHBCLK divided by 8 as ADC clock.
10100: AHBCLK divided by 12 as ADC clock.
11100: AHBCLK divided by 16 as ADC clock.
00101: AHBCLK divided by 8 as ADC clock.
01101: AHBCLK divided by 16 as ADC clock.
RW 10101: AHBCLK divided by 24 as ADC clock.
11101: AHBCLK divided by 32 as ADC clock.
00110: AHBCLK divided by 16 as ADC clock.
01110: AHBCLK divided by 32 as ADC clock.
10110: AHBCLK divided by 48 as ADC clock.
11110: AHBCLK divided by 64 as ADC clock.
00111: AHBCLK divided by 32 as ADC clock.
01111: AHBCLK divided by 64 as ADC clock.
10111: AHBCLK divided by 96 as ADC clock.
11111: AHBCLK divided by 128 as ADC clock.
Note: The ADC clock should not exceed a maximum of
24MHz.
RW Reserved
AHB clock source prescaler control.
0000: Prescaler off.
0001: SYSCLK divided by 2.
0010: SYSCLK divided by 3.
RW
0011: SYSCLK divided by 4.
0100: SYSCLK divided by 5.
0101: SYSCLK divided by 6.
0110: SYSCLK divided by 7.
18
23 22 21 20
Reserved
7 6 5 4
HPRE[3:0]
Description
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19 18 17 16
PLL
SRC
3 2 1 0
SWS[1:0] SW[1:0]
Reset
value
0
0
0
0
0
0
0