WCH CH32V003 Series Reference Manual page 138

CH32V003 Reference Manual
7 TXE
6 TC
5 RXNE
4 IDLE
3 ORE
2 NE
V1.3
cleared by software.
If LBDIE is already set, an interrupt will be
generated.
1: LIN disconnection detected.
0: No detection of pending LIN disconnection.
Send data register empty flag. This bit is set by
hardware when the data in the TDR register is
transferred to the shift register by hardware. If
TXEIE is already set, an interrupt will be
RO generated to perform a write operation to the data
register and this bit will be reset.
1: the data has been transferred to the shift register.
0: The data has not been transferred to the shift
register.
Send completion flag. When a frame containing
data is sent and TXE is set, the hardware will set
this bit, and if TCIE is set, an interrupt will be
generated, and the software will clear this bit by
RW0
reading it and then writing to the data register. It is
also possible to write 0 directly to clear this bit.
1: Sending completed.
0: Sending is not yet complete.
Read data register non-empty flag, this bit is set by
hardware when data in the shift register is
transferred to the data register. If RXNEIE is
already set, a corresponding interrupt is also
RW0 generated. A read operation of the data register
clears this bit. It is also possible to clear the bit by
writing a 0 directly.
1: Data received and able to be read out.
0: The data has not been received.
Bus idle flag. When the bus is idle, this bit will be
set by hardware. If IDLEIE is already set, the
corresponding interrupt will be generated. The
operation of reading the status register and then
RO reading the data register will clear this bit.
1: The bus is idle.
0: No bus idle is detected.
Note: This bit will not be set again until RXNE is
set.
Overload error flag. This bit will be set when there
is data in the receive shift register that needs to be
transferred to the data register, but there is still
data in the receive field of the data register that has
not been read out. If RXNEIE is set, the
corresponding interrupt will also be generated.
RO 1: Occurrence of an overload error.
0: No overload error.
Note: In case of an overload error, the value of the
data register is not lost, but the value of the shift
register is overwritten. If the EIEable bit is set, the
ORE flag position bit generates an interrupt in
multi-buffer communication mode.
Noise error flag. It is set by hardware when the
noise error flag is detected. The operation of
reading the status register and then reading the
RO data register resets this bit.
1: Noise detected.
0: No noise is detected.
Note: This bit does not generate an
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