Afio Register Description; Port Configuration Lock Register (Gpiox_Lckr) (X=A/C/D); Remap Register 1 (Afio_Pcfr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

7.3.1.6 Port configuration lock register (GPIOx_LCKR) (x=A/C/D)

Offset address: 0x18
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:9] Reserved
8 LCKK
[7:0] LCKy
Note: After the LOCK sequence is executed for the corresponding port bit, the configuration of the port bit
will not be changed again until the next system reset.

7.3.2 AFIO register description

Unless otherwise specified, AFIO registers must be operated as words (operate these registers with 32 bits).
Name
R32_AFIO_PCFR1
R32_AFIO_EXTICR

7.3.2.1 Remap Register 1 (AFIO_PCFR1)

Offset address: 0x04
31 30 29 28
Reserved
15 14 13 12
V1.3
form.
27 26 25 24
Reserved
11 10 9 8
LCKK LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0
Access
RO Reserved
The lock key, which can be written in a specific
sequence to achieve locking, but which can be
read out at any time. It reads 0 to indicate that no
locking is in effect, and reads 1 to indicate that
locking is in effect.
The write sequence for the lock key is: write 1 -
write 0 - write 1 - read 0 - read 1. The last step is
RW not necessary, but can be used to confirm that the
lock key is active.
Any error while writing the sequence will not
enable the activation of the lock and the value of
LCK[7:0] cannot be changed while the sequence
is being written. After the lock is in effect, the port
configuration can only be changed after the next
reset.
(y=0-7), these bits are 1 to indicate locking the
configuration of the corresponding port. These bits
can only be changed before the LCKK is
RW
unlocked. The locked configuration refers to the
configuration
GPIOx_CFGHR.
Table 7-16 List of AFIO-related registers
Access address
0x40010004 Remap Register 1
External
0x40010008
register 1
27 26 25 24
SWCFG[2:0]
11 10 9 8
23 22 21
7 6 5
Description
registers GPIOx_CFGLR
Description
interrupt configuration
23 22 21 20
USA
TIM1 I2C1
RT1R Reserved
_RM RM1
M1
7 6 5
58
http://wch.cn
20 19 18 17
4 3 2 1
Reset value
0
0
0
and
Reset value
0x00000000
0x00000000
19 18 17
ADC1
ADC1
_ETR
_ETR
GRE
GINJ_
G_R
RM
M
4 3 2 1
16
0
16
Reser
ved
0