I2C Own Address Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
13.11.2 I2C Control register 2(I2C1_CTLR2)
Offset address: 0x04
15 14 13 12
Reserved LAST
Bit Name
[15:13] Reserved
12 LAST
11 DMAEN
10 ITBUFEN
9 ITEVTEN
8 ITERREN
[7:6] Reserved
[5:0] FREQ
13.11.3 I2C Own address register 1(I2C1_OAR1)
Offset address: 0x08
15 14 13 12
ADD
MOD Reserved
E
Bit Name
15 ADDMODE
V1.3
11 10 9 8
DMA ITBU ITEV ITER
EN FEN TEN REN
Access
RO Reserved
DMA last transfer bit.
1：Next DMA EOT is the last transfer.
0：Next DMA EOT is not the last transfer.
RW
Note: This bit is used in master receiver mode to
permit the generation of a NACK on the last
received data.
DMA requests enable bit. Set this bit to allow
RW
DMA request when TxE or RxEN is set.
Buffer interrupt enable bit.
1：When TxE or RxEN is set, event interrupt is
RW generated.
0：When TxE or RxEN is set, no interrupt is
generated.
Event interrupt enable bit. Set this bit to enable
event interrupt. This interrupt will be generated
under the following conditions.
SB=1 (Master mode).
ADDR=1 (Master-slave mode).
RW
ADDR10 = 1 (Master mode).
STOPF=1 (Slave mode).
BTF = 1, but no TxE or RxEN events.
TxE event to 1 if ITBUFEN = 1.
RxNE event to 1if ITBUFEN = 1.
Error interrupt enable bit. Set to allow error
interrupts.
The interrupt will be generated under the
RW
following conditions.
BERR=1; ARLO=1; AF=1; OVR=1; PECERR=1.
TIMEOUT=1; SMBAlert=1.
RO Reserved
The I2C module clock frequency field, which
must be entered at the correct clock frequency to
RW produce the correct timing, allows a range
between 2-36 MHz. It must be set between
000010b and 100100b in MHz.
11 10 9 8
ADD[9:8]
Access
Address mode.
RW 1: 10-bit slave address (does not respond to 7-bit
addresses).
7 6 5
Reserved
Description
7 6 5
ADD[7:1]
Description
152
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4 3 2 1
FREQ[5:0]
Reset value
0
0
0
0
0
0
0
0
4 3 2 1
Reset value
0
0
0
ADD
0