Dma Control Register (Tim2_Dmacfgr); Dma Address Register For Continuous Mode (Tim2_Dmaadr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
[15:0] CH3CVR
11.4.16 Compare/capture register 4 (TIM2_CH4CVR)
Offset address: 0x40
15 14 13 12
Bit Name
[15:0] CH4CVR

11.4.17 DMA Control register (TIM2_DMACFGR)

Offset address: 0x48
15 14 13 12
Reserved
Bit Name
[15:13] Reserved
[12:8] DBL
[7:5] Reserved
[4:0] DBA

11.4.18 DMA Address register for continuous mode (TIM2_DMAADR)

Offset address: 0x4C
15 14 13 12
Bit Name
[15:0] DMAADR
V1.3
RW Compare the value of capture register channel 3.
11 10 9 8
CH4CVR[15:0]
Access
RW Compare the value of capture register channel 4.
11 10 9 8
DBL[4:0]
Access
RO Reserved
The length of the DMA continuous transmission, the
RW
actual value of which is the value of this field + 1.
RO Reserved
These bits define the offset of the DMA in continuous
RW mode from the address where control register 1 is
located.
11 10 9 8
DMAADR[15:0]
Access
RW The address of the DMA in continuous mode.
132
7 6 5 4
Description
7 6 5 4
Reserved
Description
7 6 5 4
Description
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0
3 2 1 0
Reset
value
0
3 2 1 0
DBA[4:0]
Reset
value
0
0
0
0
3 2 1 0
Reset
value
0