Low-Speed Clock (Lsi); Pll Clock; Bus/Peripheral Clock; Independent Watchdog Clock - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

3.3.3 Low-speed clock (LSI)

The LSI is a low-speed clock signal generated by the system's internal RC oscillator of approximately 128
KHz. It can be kept running in shutdown and standby modes and provides the clock reference for the RTC
clock, independent watchdog and wake-up unit. Further information can be found in the Electrical
Characteristics section of the datasheet. the LSI can be enabled and disabled by setting the LSION bit in the
RCC_RSTSCKR register and then detecting whether the LSI RC oscillation is stable by interrogating the
LSIRDY bit, and the hardware feeds the clock in only after LSIRDY position 1. If the LSIRDYIE bit in the
RCC_INTR register is set, the corresponding interrupt will be generated.

3.3.4 PLL clock

By configuring the RCC_CFGR0 register and the extended register EXTEND_CTR, the internal PLL clock
can select 2 clock sources, these settings must be done before PLL is turned on, once PLL is started these
parameters cannot be changed. Set the PLLON bit in the RCC_CTLR register to be enabled and disabled, the
PLLRDY bit to indicate whether the PLL clock is stable, and the hardware to feed the clock into the system
only after PLL position 1. If the PLLRDYIE bit of the RCC_INTR register is set, the corresponding interrupt
will be generated.
PLL clock source:
l HSI clock
l HSE Clock

3.3.5 Bus/Peripheral clock

3.3.5.1 System clock (SYSCLK)
Configure the system clock source by configuring the RCC_CFGR0 register SW[1:0] bits, SWS[1:0] indicates
the current system clock source.
l HSI as system clock
l HSE as system clock
l PLL as system clock
After a controller reset, the default HSI clock is selected as the system clock source. Switching between clock
sources must occur only when the target clock source is ready.
3.3.5.2 AHB/APB1/APB2 bus peripheral clock (HCLK/PCLK1/PCLK2)
The AHB, APB1, and APB2 bus clocks can be configured by configuring the HPRE[3:0], PPRE1[2:0], and
PPRE2[2:0] bits of the RCC_CFGR0 register, respectively. These bus clocks determine the peripheral interface
access clock reference that is mounted below them. Applications can adjust different values to reduce the
power consumption when some of the peripherals are operating.
The various bits in the RCC_APB1PRSTR and RCC_APB2PRSTR registers can reset the different peripheral
modules to their initial state.
Each bit in the RCC_AHBPCENR, RCC_APB1PCENR, and RCC_APB2PCENR registers can be used to
individually turn on or off the communication clock interface for different peripheral modules. When using a
peripheral, you first need to turn on its clock enable bit in order to access its registers.

3.3.5.3 Independent watchdog clock

If the standalone watchdog has been set by hardware configuration or started by software, the LSI oscillator
will be forced on and cannot be turned off. After the LSI oscillator is stabilized, the clock is supplied to the
IWDG.
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