Dma Interrupt Status Register (Dma_Intfr); Dma Interrupt Flag Clear Register (Dma_Intfcr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
R32_DMA_CNTR2
R32_DMA_PADDR2
R32_DMA_MADDR2
R32_DMA_CFGR3
R32_DMA_CNTR3
R32_DMA_PADDR3
R32_DMA_MADDR3
R32_DMA_CFGR4
R32_DMA_CNTR4
R32_DMA_PADDR4
R32_DMA_MADDR4
R32_DMA_CFGR5
R32_DMA_CNTR5
R32_DMA_PADDR5
R32_DMA_MADDR5
R32_DMA_CFGR6
R32_DMA_CNTR6
R32_DMA_PADDR6
R32_DMA_MADDR6
R32_DMA_CFGR7
R32_DMA_CNTR7
R32_DMA_PADDR7
R32_DMA_MADDR7

8.3.1 DMA Interrupt status register (DMA_INTFR)

Offset address: 0x00 + (x-1)*0x400
31 30 29 28
Reserved
15 14 13 12
TEIF HTIF TCIF
GIF4
4 4 4
Bit Name
[31:28] Reserved
27/23/19/1
TEIFx
5/11/7/3
26/22/18/1
HTIFx
4/10/6/2
25/21/17/1
TCIFx
3/9/5/1
24/20/16/1
GIFx
2/8/4/0

8.3.2 DMA Interrupt flag clear register (DMA_INTFCR)

V1.3
0x40020020 DMA channel 2 number of data register
0x40020024 DMA channel 2 peripheral address register
0x40020028 DMA channel 2 memory address register
0x40020030 DMA channel 3 configuration register
0x40020034 DMA channel 3 number of data register
0x40020038 DMA channel 3 peripheral address register
0x4002003C DMA channel 3 memory address register
0x40020044 DMA channel 4 configuration register
0x40020048 DMA channel 4 number of data register
0x4002004C DMA channel 4 peripheral address register
0x40020050 DMA channel 4 memory address register
0x40020058 DMA channel 5 configuration register
0x4002005C DMA channel 5 number of data register
0x40020060 DMA channel 5 peripheral address register
0x40020064 DMA channel 5 memory address register
0x4002006C DMA channel 6 configuration register
0x40020070 DMA channel 6 number of data register
0x40020074 DMA channel 6 peripheral address register
0x40020078 DMA channel 6 memory address register
0x40020080 DMA channel 7 configuration register
0x40020084 DMA channel 7 number of data register
0x40020088 DMA channel 7 peripheral address register
0x4002008C DMA channel 7 memory address register
27 26 25 24
TEIF HTIF TCIF
GIF7
7 7 7
11 10 9
TEIF HTIF TCIF
GIF3
3 3 3
Access
RO Reserved
Transmission error flag for channel x (x=1/2/3/4/5/6/7).
1: A transmission error occurred on channel x.
RO
0: No transmission error on channel x.
Hardware set, software write CTEIFx bit to clear this flag.
Transmission halfway flag for channel x (x=1/2/3/4/5/6/7).
1: a transmission over half event is generated on channel x.
RO
0: No transmission over half on channel x.
Hardware set, software write CHTIFx bit to clear this flag.
Transmission completion flag for channel x (x=1/2/3/4/5/6/7).
1: a transmission completion event is generated on channel x.
RO
0: No transmission completion event on channel x.
Hardware set, software write CTCIFx bit to clear this flag.
Global interrupt flag for channel x (x=1/2/3/4/5/6/7).
1: TEIFx or HTIFx or TCIFx is generated on channel x.
RO
0: No TEIFx or HTIFx or TCIFx occurred on channel x.
Hardware set, software write CGIFx bit to clear this flag.
23 22 21
TEIF HTIF TCIF
6 6 6
8 7 6 5
TEIF HTIF TCIF
2 2 2
Description
66
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0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
20 19 18 17
TEIF HTIF TCIF
GIF6
5 5 5
4 3 2 1
TEIF HTIF TCIF
GIF2
1 1 1
16
GIF5
0
GIF1
Reset
value
0
0
0
0
0