Window Watchdog (Wwdg); Enable Window Watchdog - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 5 Window Watchdog (WWDG)
A Window Watchdog is generally used to monitor system operation for software faults such as external
disturbances, unforeseen logic errors, and other conditions. It requires a counter refresh (dog feeding) within
a specific window time (with upper and lower limits), otherwise earlier or later than this window time the
watchdog circuit will generate a system Reset.
5.1 Main features
l Programmable 7-bit downcounter
l Biconditional reset: the downcounter value is less than 0x40, or the counter value is reloaded outside the
window time
l Wake Up Early Notification (EWI) function for timely dog feeding action to prevent system Reset
5.2 Function description
5.2.1 Principle and application
The window watchdog operation is based on a 7-bit downcounter, which is mounted under the APB1 bus and
counts the dividing frequency of the time base WWDG_CLK source (PCLK1/4096) clock with the dividing
factor set in the WDGTB[1:0] field in the configuration register WWDG_CFGR. The downcounter is in the
free-running state, and the counter keeps cycling downcount regardless of whether the watchdog function is
on or not. As shown in Figure 5-1, the block diagram of the internal structure of the window watchdog.
RESET
WWDG enable control, software on
l

Enable Window Watchdog

After a system Reset, the watchdog is off. Setting the WDGA bit of the WWDG_CTLR register enables the
watchdog, and then it cannot be turned off again unless a reset occurs.
Note: The watchdog function can be stopped indirectly by setting the RCC_APB1PCENR register to turn off
the clock source of WWDG and suspend the WWDG_CLK count, or by setting the RCC_APB1PRSTR
register to reset the WWDG module, which is equivalent to the role of reset.
l Watchdog Configuration
The watchdog is internally a 7-bit counter that runs in a continuous decreasing cycle and supports read and
write access. To use the watchdog reset function, the following actions need to be performed.
1) Counting time base: via the WDGTB[1:0] bit field of the WWDG_CFGR register, note that the WWDG
module clock of the RCC unit should be turned on.
2) Window counter: Set the W[6:0] bit field of WWDG_CFGR register, this counter is used by hardware as
V1.3
Figure 5-1 Block diagram of Window Watchdog structure
T[6:0] W[6:0]
＞
Write WWDG_CTLR[6:0]
PCLK1
Watchdog configuration register(WWDG_CFGR)
-
W6 W5 W4 W3 W2 W1 W0
Watchdog control register(WWDG_CTLR)
WDGA T6 T5 T4 T3 T2 T1 T0
/4096
WDGTB[1:0]
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WWDG_CLK