Dma Channel X Configuration Register (Dma_Cfgrx) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Offset address: 0x04 + (x-1)*0x400
31 30 29 28
Reserved
15 14 13 12
CTEIF CHTIF CTCIF CGIF
4 4 4 4
Bit Name
[31:28] Reserved
27/23/19/1
CTEIFx
5/11/7/3
26/22/18/1
CHTIFx
4/10/6/2
25/21/17/1
CTCIFx
3/9/5/1
24/20/16/1
CGIFx
2/8/4/0
8.3.3 DMA Channel x configuration register (DMA_CFGRx)(x=1/2/3/4/5/6/7)
Offset address: 0x08 + (x-1)*20 + (y-1)*0x400
31 30 29 28
15 14 13 12
MEM
Reser
2 PL[1:0]
ved
MEM
Bit Name
[31:15] Reserved
14 MEM2MEM
[13:12] PL
[11:10] MSIZE
[9:8] PSIZE
V1.3
27 26 25 24
CTEIF CHTIF CTCIF CGIF
7 7 7 7
11 10 9 8
CTEIF CHTIF CTCIF CGIF
3 3 3 3
Access
RO Reserved
Clear the transmission error flag for channel x
(x=1/2/3/4/5/6/7).
WO
1: Clear the TEIFx flag in the DMA_INTFR register.
0: No effect.
Clear the transmission halfway flag for channel x
(x=1/2/3/4/5/6/7).
WO
1: Clear the HTIFx flag in the DMA_INTFR register.
0: No effect.
Clear the transmission completion flag for channel x
(x=1/2/3/4/5/6/7).
WO 1: Clear the TCIFx flag in the DMA_INTFR
register.
0: No effect.
Clear the
(x=1/2/3/4/5/6/7).
WO 1: Clear the TEIFx/HTIFx/TCIFx/ GIFx flags in the
DMA_INTFR register.
0: No effect.
27 26 25 24
Reserved
11 10 9 8
MSIZE[1:0] PSIZE[1:0]
Access
RO Reserved
Memory-to-memory mode enable.
RW 1: Enable memory-to-memory data transfer mode.
0: Disable memory-to-memory data transfer mode.
Channel priority setting.
RW 00: low; 01: medium.
10: High; 11:Very high.
Memory address data width setting.
RW 00: 8 bits; 01: 16 bits.
10: 32 bits; 11: Reserved.
Peripheral address data width setting.
RW 00: 8 bits; 01: 16 bits.
10: 32 bits; 11: Reserved.
23 22 21
CTEIF CHTIF CTCIF CGIF
6 6 6
7 6 5
CTEIF CHTIF CTCIF CGIF
2 2 2
Description
global interrupt flag
23 22 21
7 6 5
MIN
PINC CIRC DIR TEIE HTIE TCIE EN
C
Description
67
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20 19 18 17
CTEIF CHTIF CTCIF
6 5 5 5
4 3 2 1
CTEIF CHTIF CTCIF
2 1 1 1
Reset
value
for channel x
20 19 18 17
4 3 2 1
Reset
value
16
CGIF
5
0
CGIF
1
0
0
0
0
0
16
0
0
0
0
0
0