System Count Status Register (Stk_Sr); System Counter Register (Stk_Cntl) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Bit Name
31 SWIE
[30:4] Reserved
3 STRE
2 STCLK
1 STIE
0 STE

6.5.4.2 System count status register (STK_SR)

Offset address: 0x04
31 30 29 28
15 14 13 12
Bit Name
[31:1] Reserved
0 CNTIF

6.5.4.3 System counter register (STK_CNTL)

Offset address: 0x08
31 30 29 28
15 14 13 12
Bit Name
[31:0] CNT
V1.3
Access
Software interrupt trigger enable (SWI).
1: Triggering software interrupts.
RW 0: Turn off the trigger.
After entering software interrupt, software clear 0 is
required, otherwise it is continuously triggered.
RO Reserved
Auto-reload count enable bit.
1: Re-counting from 0 after counting up to the
comparison value.
RW
0: Count up to the comparison value and continue
counting up, count down to 0 and start counting down
again from the maximum value.
Counter clock source selection bit.
RW 1: HCLK for time base.
0: HCLK/8 for time base.
Counter interrupt enable control bit.
RW 1: Enabling counter interrupts.
0: Turn off the counter interrupt.
System counter enable control bit.
1: Start the system counter STK.
RW
0: Turn off the system counter STK and the counter
stops counting.
27 26 25 24
Reserved
11 10 9 8
Reserved
Access
RO Reserved
Count value comparison flag, write 0 to clear, write 1 to
invalidate.
RW0
1: Up count reaches the comparison value.
0: The comparison value is not reached.
27 26 25 24
CNT[31:16]
11 10 9 8
CNT[15:0]
Access
RW The current counter count value is 32 bits.
Description
23 22 21
7 6 5
Description
23 22 21
7 6 5
Description
48
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Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
16
0
CNTI
F
16
0