Control Register 2 (Tim1_Ctlr2) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
1 UDIS
0 CEN

10.4.2 Control Register 2 (TIM1_CTLR2)

Offset address: 0x04
15 14 13
Reserved OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Reserved CCPC
Bit Name
15 Reserved
14 OIS4
13 OIS3N
12 OIS3
11 OIS2N
10 OIS2
9 OIS1N
8 OIS1
7 TI1S
[6:4] MMS
V1.3
update interrupt or DMA request is generated by any of
the following events.
-Counter overflow/underflow
-Setting the UG position
-Updates generated from the mode controller
Disable updates, the software allows/disables the
generation of UEV events by means of this bit.
1: UEV is disabled. no update event is generated and
the registers (ARR, PSC, CCRx) keep their values. If
the UG bit is set or a hardware reset is issued from the
mode controller, the counters and prescaler are
reinitialized.
RW
0: UEV is allowed. update (UEV) events are generated
by any of the following events:
-Counter overflow/underflow
-Setting the UG position
-Updates generated from the mode controller
Registers with caches are loaded with their preloaded
values.
Enables the counter.
1: Enables the counter.
0: Disable the counter.
RW Note: The external clock, gated mode and encoder
mode will not work until the CEN bit is set in software.
Trigger mode can automatically set the CEN bit in
hardware.
12 11 10 9
Access
RO Reserved
Output idle state 4.
1: When MOE=0, if OC4N is implemented, OC1=1
after deadband;
RW 0: When MOE=0, if OC4N is implemented, OC1=0
after deadband.
Note: This bit cannot be modified after LOCK
(TIMx_BDTR register) level 1, 2 or 3 has been set.
Output idle state 3.
1: OC1N = 1 after the dead zone when MOE = 0.
RW 0: When MOE=0, OC1N=0 after dead zone.
Note: This bit cannot be modified after the LOCK
(TIMx_BDTR register) level 1, 2 or 3 has been set.
RW Output idle state 3, see OIS4.
RW Output idle state 2, see OIS3N.
RW Output idle state 2, see OIS4.
RW Output idle state 1, see OIS3N.
RW Output idle state 1, see OIS4.
TI1 selection.
1: TIMx_CH1, TIMx_CH2 and TIMx_CH3 pins
RW
connected to TI1 input after heterodyning.
0: TIMx_CH1 pin is connected directly to TI1 input.
RW Master mode selection:These 3 bits are used to select
8 7 6 5 4
Description
97
http://wch.cn
0
0
3 2 1
Reset
value
0
0
0
0
0
0
0
0
0
0
0