Spi1 Transmit Crc Register (Spi1_Tcrcr); Spi High-Speed Control Register (Spi1_Hscr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

14.3.7 SPI1 Transmit CRC register (SPI1_TCRCR)

Offset address: 0x18
15 14 13 12
Bit Name
[15:0] TXCRC

14.3.8 SPI High-speed control register (SPI1_HSCR)

Offset address: 0x24
15 14 13 12
Bit
[15:1] Reserved
0 HSRXEN
V1.3
checksum of the received byte. Setting CRCEN
resets this register. The calculation method uses
the polynomial used in CRCPOLY. 8-bit mode
only the lower 8 bits are involved in the
calculation, 16-bit mode all 16 bits are involved in
the calculation. It is necessary to read this register
when BSY is 0.
11 10 9
Access
Tx CRC. Store the result of the calculated CRC
checksum of the bytes that have been sent out.
Setting
calculation method uses the polynomial used in
RO
CRCPOLY. 8-bit mode only the lower 8 bits are
involved in the calculation, while in 16-bit mode
all 16 bits are involved. It is necessary to read this
register when BSY is 0.
11 10 9
Reserved
Name Access
RO
WO
8 7 6 5
TXCRC
Description
CRCEN resets this
8 7 6 5
Description
Reserved
Read enable in SPI high-speed mode (CLK greater than
or equal to 36 MHz). This mode is valid only when the
clock is divided by 2 (i.e., BR = 000 in the CTLR1
register). This bit is not readable.
1: Enable high-speed read mode.
0: Disable high-speed read mode.
164
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4 3 2 1
Reset value
register. The
0
4 3 2 1
0
0
HSR
X
EN