WCH CH32V003 Series Reference Manual page 123

CH32V003 Reference Manual
7 MSM
[6:4] TS
3 Reserved
[2:0] SMS
11.4.4 Slave mode control register (TIM2_SMCFGR)
Offset address: 0x0C
15 14 13
V1.3
0110: sampling frequency Fsampling = Fdts/4, N = 6.
0111: sampling frequency Fsampling = Fdts/4, N = 8.
1000: sampling frequency Fsampling = Fdts/8, N = 6.
1001: sampling frequency Fsampling = Fdts/8, N = 8.
1010: sampling frequency Fsampling = Fdts/16, N = 5.
1011: sampling frequency Fsampling = Fdts/16, N = 6.
1100: sampling frequency Fsampling = Fdts/16, N = 8.
1101: sampling frequency Fsampling = Fdts/32, N = 5.
1110: sampling frequency Fsampling = Fdts/32, N = 6.
1111: Sampling frequency Fsampling=Fdts/32, N=8.
Master/slave mode selection.
1: The event on the trigger input (TRGI) isdelayed to
allow perfect synchronization between the current timer
RW (via TRGO) and its slave timer. This is useful when the
synchronization of several timers to a single external
event is required.
0: Does not function.
Trigger select field, these 3 bits select the trigger input
source used to synchronize the counter.
000: Internal trigger 0 (ITR0).
100: Edge detector of TI1 (TI1F_ED).
001: Internal trigger 1 (ITR1).
RW 101: Filtered timer input 1 (TI1FP1).
010: Internal trigger 2 (ITR2).
110: Filtered timer input 2 (TI2FP2).
011: Internal trigger 3 (ITR3).
111: External trigger input (ETRF).
The above only changes when SMS is 0.
RO Reserved
Input mode selection field. Selects the clock and trigger
mode of the core counter.
000: driven by the internal clock CK_INT.
001: encoder mode 1, where the core counter
increments or decrements the count at the edge of
TI2FP2 depending on the level of TI1FP1.
010: encoder mode 2, where the core counter
increments or decrements the count at the edge of
TI1FP1, depending on the level of TI2FP2.
011: encoder mode 3, where the core counter
increments and decrements the count on the edges of
TI1FP1 and TI2FP2 depending on the input level of
RW another signal;
100: reset mode, where the rising edge of the trigger
input (TRGI) will initialize the counter and generate a
signal to update the registers.
101: Gated mode, when the trigger input (TRGI) is
high, the counter clock is turnedon; at the trigger input
becomes low, the counter is stopped, and the counter
starts and stops are controlled.
110: Trigger mode, where the counter is started on the
rising edge of the trigger input TRGI and only the start
of the counter is controlled.
111: External clock mode 1, rising edge of the selected
trigger input (TRGI) drives the counter.
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