Dma-Related Registers List; Dma1 Request Image; Dma1 Peripheral Mapping Table For Each Channel - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Peripherals Channel1
ADC1 ADC1
SPI1
USART1
I2C1
TIM1
TIM2 TIM2_CH3
8.3 Register description
Name
R32_DMA_INTFR
R32_DMA_INTFCR
R32_DMA_CFGR1
R32_DMA_CNTR1
R32_DMA_PADDR1
R32_DMA_MADDR1
R32_DMA_CFGR2
V1.3
Figure 8-1 DMA1 request image
Table 8-2 DMA1 peripheral mapping table for each channel
Channel 2 Channel 3
SPI1_RX SPI1_TX
TIM1_CH1 TIM1_CH2
TIM2_UP
Table 8-3 DMA-related registers list
Access address
0x40020000 DMA interrupt status register
0x40020004 DMA interrupt flag clear register
0x40020008 DMA channel 1 configuration register
0x4002000C DMA channel 1 number of data register
0x40020010 DMA channel 1 peripheral address register
0x40020014 DMA channel 1 memory address register
0x4002001C DMA channel 2 configuration register
Channel 4 Channel 5
USART1_TX USART1_RX
TIM1_CH4
TIM1_TRIG TIM1_UP
TIM1_COM
TIM2_CH1
Description
65
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Channel 6 Channel 7
I2C1_TX I2C1_RX
TIM1_CH3
TIM2_CH2
TIM2_CH4
Reset value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000