Direct Memory Access Control (Dma); Dma Channel Processing; Arbitration Priority; Dma Configuration - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Chapter 8 Direct Memory Access Control (DMA)
Direct Memory Access Controller (DMA) provides a high-speed data transfer method between peripherals and
memory or between memory and memory without CPU intervention, and data can be moved quickly through
DMA to save CPU resources for other operations.
Each channel of the DMA controller is dedicated to managing requests for memory access from one or more
peripherals. There is also an arbiter to coordinate the priority between the channels.
8.1 Main features
l Multiple independently configurable channels
l Each channel is directly connected to a dedicated hardware DMA request and supports software triggering
l Buffer management with loop support
l Request priority between multiple channels can be set by software programming (very high, high,
medium and low) and priority setting is determined by the channel number when equal (the lower the
channel number the higher the priority)
l
Supports peripheral-to-memory, memory-to-peripheral, and memory-to-memory transfers
l Flash memory, SRAM, peripheral SRAM, APB1, APB2 and AHB peripherals can be used as access
sources and targets
l
Programmable number of data transfers: up to 65535
8.2 Function description

8.2.1 DMA channel processing

1)

Arbitration priority

DMA requests generated by multiple independent channels are fed to the DMA controller via a logical or
structure, and only one channel request is currently responded to. An arbiter inside the module selects the
peripheral/memory access to be initiated based on the priority of the channel request.
In software management, the application can configure the priority level for each channel independently by
setting the PL[1:0] bits of the DMA_CFGRx register, including four levels: highest, high, medium and low.
When the software setting levels are the same between channels, the module will be selected according to a
fixed hardware priority, with the lower channel number having a higher priority than the higher one.
2)

DMA configuration

When the DMA controller receives a request signal, it accesses the requested peripheral or memory and
establishes a data transfer between the peripheral or memory and the memory. It consists of the following 3
main operation steps.
(1) Fetch data from the memory address indicated by the Peripheral Data Register or the Current
Peripheral/Memory Address Register. The start address for the first transfer is the peripheral base address
or memory address specified by the DMA_PADDRx or DMA_MADDRx registers.
(2) Store data to the memory address indicated by the Peripheral Data Register or the Current
Peripheral/Memory Address Register, and the start address for the first transfer is the peripheral base
address or memory address specified by the DMA_PADDRx or DMA_MADDRx registers.
(3) Performs a decrement operation of the value in the DMA_CNTRx register, which indicates the number
of operations currently outstanding for transfer.
Each channel includes 3 types of DMA data transfer methods.
l Peripheral to memory (MEM2MEM=0, DIR=0)
l
Memory to peripheral (MEM2MEM=0, DIR=1)
l Memory to memory (MEM2MEM=1)
Note: The memory-to-memory mode does not require a peripheral request signal. After configuring this mode
V1.3 62
http://wch.cn