Clock Interrupt Register (Rcc_Intr) - WCH CH32V003 Series Reference Manual

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CH32V003 Reference Manual
[3:2]
SWS
[1:0]
SW

3.4.3 Clock interrupt register (RCC_INTR)

Offset address: 0x04
31
30
29
28
Reserved
15
14
13
12
PLL
Reserved
RDYI
E
Bit
Name
[31:24]
Reserved
23
CSSC
[22:21]
Reserved
20
PLLRDYC
19
HSERDYC
18
HSIRDYC
17
Reserved
16
LSIRDYC
V1.3
0111: SYSCLK divided by 8.
1000: SYSCLK divided by 2.
1001: SYSCLK divided by 4.
1010: SYSCLK divided by 8.
1011: SYSCLK divided by 16.
1100: SYSCLK divided by 32.
1101: SYSCLK divided by 64.
1110: SYSCLK divided by 128.
1111: SYSCLK divided by 256.
Note: When the prescaler factor of the AHB clock source is
greater than 1, the prefetch buffer must be turned on.
System clock (SYSCLK) status (hardware set).
00: the system clock source is HSI.
RO
01: The system clock source is HSE.
10: The system clock source is a PLL.
11: Not available.
Select the system clock source.
00: HSI as system clock.
01: HSE as system clock.
10: PLL output as system clock.
RW
11: Not available.
Note: With Clock Safe enabled (CSSON=1), HSI is forced
by hardware to be selected as the system clock when
returning from Standby and Stop mode or when the
external oscillator HSE used as the system clock fails.
27
26
25
11
10
9
HSE
HSI
Reserv
RDYI
RDYI
ed
RDYIE
E
E
Access
RO
Reserved
Clear the clock security system interrupt flag bit (CSSF).
WO
1: Clear the CSSF interrupt flag.
0: No action.
RO
Reserved
Clear the PLL-ready interrupt flag bit.
WO
1: Clear the PLLRDYF interrupt flag.
0: No action.
Clear the HSE oscillator ready interrupt flag bit.
WO
1: Clear the HSERDYF interrupt flag.
0: No action.
Clear the HSI oscillator ready interrupt flag bit.
WO
1: Clear the HSIRDYF interrupt flag.
0: No action.
RO
Reserved
Clear the LSI oscillator ready interrupt flag bit.
WO
1: Clear the LSIRDYF interrupt flag.
24
23
22
21
CS
Reserved
SC
8
7
6
5
LSI
CS
Reserved
SF
Description
19
http://wch.cn
20
19
18
17
PLL
HSE
HSI
Reser
RDY
RDY
RDY
ved
C
C
C
4
3
2
1
PLL
HSE
HSI
Reser
RDY
RDY
RDY
ved
F
F
F
0
0
16
LSI
RDY
C
0
LSI
RDY
F
Reset
value
0
0
0
0
0
0
0
0

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