WCH CH32V003 Series Reference Manual page 96

CH32V003 Reference Manual
14 TMR_CAP_OV_EN
[13:10] Reserved
[9:8] CKD
7 ARPE
[6:5] CMS
4 DIR
3 OPM
2 URS
V1.3
0: Turn off the indication function
1: Enables the indication function.
Note: When enabled, [16] of CHxCVR indicates the
level corresponding to the capture value.
Capture value mode configuration.
0: The capture value is the value of the actual counter
RW
1: The CHxCVR value is 0xFFFF when a counter
overflow is generated before capture.
RO Reserved
These 2 bits define the division ratio between the timer
clock (CK_INT) frequency, the dead time and the
sampling clock used by the dead time generator and the
digital filter (ETR,TIx).
RW
00: Tdts=Tck_int
01: Tdts = 2 x Tck_int
10: Tdts = 4 x Tck_int
11: Reserved.
Auto-reload preload enable bit.
1: Enables the Automatic Reload Value Register
RW
(ATRLR).
0: Auto Reload Value Register (ATRLR) is disabled.
Central alignment mode selection.
00: Edge-aligned mode. The counter counts up or down
based on the direction bit (DIR).
01: Central alignment mode 1. The counter counts up
and down alternately. The output compare interrupt flag
bit of the channel configured as output (CCxS=00 in the
CHCTLRx register) is set only when the counter counts
down.
10: Central alignment mode 2. The counter counts up
and down alternately. The output compare interrupt flag
RW bit of the channel configured as output (CCxS=00 in the
CHCTLRx register) is set only when the counter counts
up.
11: Central alignment mode 3. The counter counts up
and down alternately. The output compare interrupt flag
bit of the channel configured as output (CCxS=00 in the
CHCTLRx register) is set when the counter counts both
up and down.
Note: When the counter is enabled (CEN=1), the
transition from edge-aligned mode to center-aligned
mode is not allowed.
Counting direction.
0: the counter's counting mode is incremental.
1: The counting mode of the counter is decimal
RW
counting.
Note: This bit is not valid when the counter is
configured in central alignment mode or encoder mode.
Single pulse mode.
1: The counter stops when the next update event
RW (clearing the CEN bit) occurs.
0: The counter does not stop when the next update event
occurs.
Update request source, by which the software selects
the source of the UEV event.
1: If an update interrupt or DMA request is enabled,
RW
only an update interrupt or DMA request is generated if
the counter overflows/underflows.
0: If an update interrupt or DMA request is enabled, an
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