Clock Input; Internal Clock Source (Ck_Int); External Clock Source Mode1/2; Block Diagram Of Ck_Psc Source For Advanced-Control Timer - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

10.2.2 Clock input

Figure 10-2 Block diagram of CK_PSC source for advanced-control timer
TI2
Filter
ICF[3:0]
TIMx_CCMR1
ETR
ETR pin
ETP
TIMx_SMCR
The advanced-control timer CK_PSC has many clock sources and can be divided into 4 categories.
1) The advanced-control timer CK_PSC has many clock sources and can be divided into 4 categories.
2) Internal APB clock input route: CK_INT.
3) Route from the comparison capture channel pin (TIMx_CHx): TIMx_CHx → TIx → TIxFPx, this route
is also used in encoder mode.
4) Inputs from other internal timers: ITRx.
The actual operation can be divided into 4 categories by determining the choice of input pulse for the SMS of
the CK_PSC source.
1) Selection of the internal clock source (CK_INT).
2) External clock source mode 1.
3) External clock source mode 2.
4) Encoder mode.
All 4 clock source sources mentioned above can be selected by these 4 operations.

10.2.2.1 Internal clock source (CK_INT)

If the SMS field is held at 000b to start the advanced-control timer, then it is the internal clock source (CK_INT)
that is selected as the clock. At this point CK_INT is CK_PSC.
10.2.2.2 External clock source mode1
When the SMS domain is set to 111b, external clock source mode 1 is enabled. When external clock source 1
is enabled, TRGI is selected as the source of CK_PSC. it is worth noting that the source of TRGI also needs
to be selected by configuring the TS domain. the TS domain can select the following types of pulses as clock
sources.
1) Internal trigger (ITRx, x is 0,1,2,3).
2) Comparison of the signal after capturing channel 1 through the edge detector (TI1F_ED).
3) Comparison of signals TI1FP1, TI2FP2 of the capture channel.
4) The signal ETRF from the external clock pin input.
10.2.2.3 External clock source mode2
Use external trigger mode 2 to count on every rising or falling edge of the external clock pin input. When the
V1.3
TI2F_Rising
0
Edge
detector
1
TI2F_Falling
CC2P
TIMx_CCER
0
Divider
ETRP
/1,/2,/4,/8
1
f
DTS
ETPS[1:0]
TIMx_SMCR
TIMx_SMCR
TS[2:0]
ITRx
0xx
TI1_ED
or
TI2F
100
or
or
TI1F
TI1FP1
101
TI2FP2
110
ETRF
111
TRGI
ETRF
Filter
CK_INT
downcounter
(internal clock)
ETF[3:0]
TIMx_SMCR
88
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Encoder
mode
External clock
mode 1
CK_PSC
External clock
mode 2
Internal clock
mode
SMS[2:0]
ECE
TIMx_SMCR