Errors; Spi-Related Registers List; Master Mode Fault (Modf) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

14.2.7 Errors

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Master mode fault (MODF)

When the SPI is operating in NSS pin hardware management mode, an external pull-down of the NSS pin
occurs; or in NSS pin software management mode, the SSI bit is cleared; or the SPE bit is cleared, causing the
SPI to be shut down; or the MSTR bit is cleared and the SPI enters slave mode. If the ERRIE bit is already set,
an interrupt is also generated. Steps to clear the MODF bit: First perform a read or write operation to
R16_SPI1_STATR, and then write R16_SPI1_CTLR1.
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Overrun condition
If the host sends data and there is unread data in the receive buffer of the slave device, an overflow error occurs,
the OVR bit is set, and an interrupt is also generated if ERRIE is set. Sending an overflow error should restart
the current transmission. Reading the data register and then reading the status register will eliminate this bit.
l CRC error
When the received CRC word and the value of RXCRCR do not match, a CRC error will be generated and the
CRCERR bit will be set.
14.2.8 Interrupts
The SPI module supports five interrupt sources, among which the TXE and RXNE events are set when the
TXEIE and RXNEIE bits are set respectively. In addition to the above three errors will also generate interrupts,
namely MODF, OVR and CRCERR, after enabling the ERRIE bit, these three errors will also generate error
interrupts.
14.3 Register description
Name
R16_SPI_CTLR1
R16_SPI_CTLR2
R16_SPI_STATR
R16_SPI_DATAR
R16_SPI_CRCR
R16_SPI_RCRCR
R16_SPI_TCRCR
R16_SPI_HSCR
14.3.1 SPI Control register 1 (SPI1_CTLR1)
Offset address: 0x00
15 14 13 12
BIDI CRC
BIDI CRC
MOD NEX
OE EN
E T
Bit Name
15 BIDIMODE
14 BIDIOE
13 CRCEN
V1.3
Table 14-1 SPI-related registers list
Access address
0x40013000 SPI Control register1
0x40013004 SPI Control register2
0x40013008 SPI Status register
0x4001300C SPI Data register
0x40013010 SPI Polynomial register
0x40013014 SPI Receive CRC register
0x40013018 SPI Transmit CRC register
0x40013024 SPI High-speed control register
11 10 9 8
RX
DFF ONL SSM SSI
Y
Access
Bidirectional data mode enable bit.
RW 1: Selection of 1-line bidirectional mode.
0: Selection of 2-line bi-directional mode.
Output enable in bidirectional mode bit, used in
conjunction with BIDImode.
RW
1: Enable output, transmit only.
0: Disable output, receive only.
Hardware CRC checksum enable bit, this bit can
RW only be written when SPE is 0. This bit can only
be used in full duplex
Description
7 6 5
Reser
SPE BR[2:0]
ved
Description
160
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Reset value
0x0000
0x0000
0x0002
0x0000
0x0007
0x0000
0x0000
0x00
4 3 2 1
MST CPO
R L
Reset value
0
0
0
0
CPH
A