External Interrupt And Event Controller (Exti); Wake-Up Event; External Interrupt (Exti) Interface Block Diagram - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
29 15 programmable
30 16 programmable
31 17 programmable
32 18 programmable
33 19 programmable
34 20 programmable
35 21 programmable
36 22 programmable
37 23 programmable
38 24 programmable

6.4 External interrupt and event controller (EXTI)

6.4.1 Overview
PCLK2
To NVIC interrupt
controller
10
generator
10
As can be seen from Figure 6-1, the trigger source of the external interrupt can be either a software interrupt
(SWIEVR) or an actual external interrupt channel. The signal of the external interrupt channel will be screened
by the edge detect circuit first. Whenever one of the software interrupt or external interrupt signals is generated,
it will be output to two with-gate circuits, event enable and interrupt enable, through the or-gate circuit in the
figure, as long as an interrupt is enabled or an event is enabled, an interrupt or an event will be generated. six
registers of EXTI are accessed by the processor through the APB2 interface.

6.4.2 Wake-up event

The system can wake up the Sleep mode caused by the WFE command through a wake-up event. The wake-
up event is generated by either of the following two configurations.
l Enabling an interrupt in a peripheral register, but not enabling this interrupt in the PFIC of the core, and
enabling the SEVONPEND bit in the core at the same time. Embodied in EXTI, it is to enable an EXTI
interrupt, but not to enable the EXTI interrupt in PFIC, and to enable the SEVONPEND bit at the same
time. When the CPU wakes up from WFE, it needs to clear the EXTI interrupt flag bit and the PFIC
V1.3
ADC
I2C1_EV
I2C1_ER
USART1
SPI1
TIM1BRK
TIM1UP
TIM1TRG
TIM1CC
TIM2
Figure 6-1 External interrupt (EXTI) interface block diagram
10
Pending Interrupt
request mask
register register
Pulse
10
Event
mask
register
ADC global Interrupt
I2C1 event interrupt
I2C1 error interrupt
USART1 global interrupt
SPI1 global Interrupt
TIM1 brake interrupt
TIM1 update interrupt
TIM1 triggers an interrupt
TIM1 captures the compare interrupt
TIM2 global interrupt
AMBA APBbus
Peripheral interface
10 10 10
Software Rising
interrupt trigger
event selection
register register
10
10 10
Edge detect
10
33
0x00000074
0x00000078
0x0000007C
0x00000080
0x00000084
0x00000088
0x0000008C
0x00000090
0x00000094
0x00000098
10
Falling
trigger
selection
register
10
Input
Line
circuit
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