Interrupt Enable Register (Exti_Intenr); Event Enable Register (Exti_Evenr); Rising Edge Trigger Enable Register (Exti_Rtenr); Falling Edge Trigger Enable Register (Exti_Ftenr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

6.5.1.1 Interrupt enable register (EXTI_INTENR)

Offset address: 0x00
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] MRx

6.5.1.2 Event enable register (EXTI_EVENR)

Offset address: 0x04
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] MRx

6.5.1.3 Rising edge trigger enable register (EXTI_RTENR)

Offset address: 0x08
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
[9:0] TRx

6.5.1.4 Falling edge trigger enable register (EXTI_FTENR)

Offset address: 0x0C
31 30 29 28
15 14 13 12
V1.3
27 26 25 24
Reserved
11 10 9 8
MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
Access
RO Reserved
Enable the interrupt request signal for external
interrupt channel x.
RW
1: Enables interrupts for this channel.
0: Mask interrupts for this channel.
27 26 25 24
Reserved
11 10 9 8
MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0
Access
RO Reserved
Enable the event request signal for external
interrupt channel x.
RW
1: Event enabling this channel.
0: Block the events of this channel.
27 26 25 24
Reserved
11 10 9 8
TR9 TR8 TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
Access
RO Reserved
Enable rising edge triggering of external interrupt
channel x.
RW
1: Enable rising edge triggering of this channel.
0: Disable rising edge triggering for this channel.
27 26 25 24
Reserved
11 10 9 8
23 22 21
7 6 5
Description
23 22 21
7 6 5
Description
23 22 21
7 6 5
Description
23 22 21
7 6 5
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20 19 18 17
4 3 2 1
Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
0
20 19 18 17
4 3 2 1
Reset value
0
0
20 19 18 17
4 3 2 1
16
0
16
0
16
0
16
0