Dma/Interrupt Enable Register (Tim1_Dmaintenr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
3 Reserved
[2:0] SMS

10.4.4 DMA/interrupt enable register (TIM1_DMAINTENR)

Offset address: 0x0C
15 14 13
Reserve TD COMD
d E E
Bit Name
15 Reserved
14 TDE
13 COMDE
12 CC4DE
11 CC3DE
V1.3
101: Filtered timer input 1 (TI1FP1).
110: Filtered timer input 2 (TI2FP2).
111: External trigger input (ETRF).
The above only changes when SMS is 0.
Note: See Table 10-2 for details.
RO Reserved
Input mode selection field. Selects the clock and trigger
mode of the core counter.
000: driven by the internal clock CK_INT.
001: encoder mode 1, where the core counter
increments or decrements the count at the edge of
TI2FP2 depending on the level of TI1FP1.
010: encoder mode 2, where the core counter
increments or decrements the count at the edge of
TI1FP1, depending on the level of TI2FP2.
011: encoder mode 3, where the core counter
increments and decrements the count on the edges of
TI1FP1 and TI2FP2 depending on the input level of
RW
another signal; 100: reset mode, where the rising edge
of the trigger input (TRGI) will initialize the counter
and generate a signal to update the registers.
101: Gated mode, when the trigger input (TRGI) is
high, the counter clock is turned on; at the trigger input
becomes low, the counter is stopped, and the counter
starts and stops are controlled.
110: trigger mode, where the counter is started on the
rising edge of the trigger input TRGI and only the start
of the counter is controlled.
111: External clock mode 1, rising edge of the selected
trigger input (TRGI) drives the counter.
12 11 10
CC4D CC3D CC2D CC1D
E E E
Access
RO Reserved
Trigger the DMA request enable bit.
RW 1: Allowing DMA requests to be triggered.
0: Triggering of DMA requests is prohibited.
DMA request enable bit of COM.
RW 1: Allow DMA requests for COM.
0: DMA request for COM is disabled.
Compare the DMA request enable bit of capture
channel 4.
1: allows comparison of DMA requests for capture
RW
channel 4.
0: Disable comparison of DMA requests for capture
channel 4.
Compare the DMA request enable bit of capture
channel 3.
RW 1: allows comparison of DMA requests for capture
channel 3.
0: Disable comparison of DMA requests for capture
9 8 7 6 5
UD BI TI COMI
E E E E E
Description
100
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4 3 2 1
CC4I CC3I CC2I CC1I
E E E E
Reset
value
0
0
0
UI
E
0
0
0
0b
0