System Clock Structure - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
3.3 Clock

3.3.1 System clock structure

128kHz
LSI RC
4~25MHz
OSC_IN
HSE OSC
OSC_OUT
MCO[1:0]
HSI
MCO
HSE
PLLCLK
V1.3
Figure 3-2 CH32V003 clock tree block diagram
to gpio(internal,to time)
IWDGCLK
to independent watchdog
to pwr(low power clock source)
RCC_CFGR0
/3
24MHz
HSI
HSI RC
AHB prescaler
/1,/2.../256
HCLK
48MHz max
peripheral clock enable
peripheral clock enable
peripheral clock enable
peripheral clock enable
peripheral clock enable
13
SW
*2
PLLSRC
SYSCLK
to Flash(time base)
SW
CSS
to Flash（register）
FCLK core free running clock
to Core System Timer
/8
to SRAM/DMA
to AHB peripherals
to TIM2
to TIM1
/2,/4,/6,/8,/12,/1
ADCPRE
6...,/64,/96,/128
to IWDG
http://wch.cn
to ADC