Packet Error Checking; I2C-Related Registers List; I2C Control Register - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual

13.10 Packet error checking

Packet Error Checksum (PEC) is an additional CRC8 checksum step to provide transmission reliability,
calculated for each bit of serial data using the following polynomial.
The PEC calculation is activated by the ENPEC bit in the control register and is performed on all information
bytes, including address and read/write bits. In transmitting, enabling PEC adds a byte of CRC8 calculation
result after the last byte of data; while in receiving mode, in the last byte is considered as CRC8 check result,
and if it does not match with the internal calculation result, it will reply a NAK, and in case of the main receiver,
regardless of the correct check result.
13.11 Register description
Name
R16_I2C_CTLR1
R16_I2C_CTLR2
R16_I2C_OADDR1
R16_I2C_OADDR2
R16_I2C_DATAR
R16_I2C_STAR1
R16_I2C_STAR2
R16_I2C_CKCFGR
13.11.1 I2C Control register 1(I2C1_CTLR1)
Offset address: 0x00
15 14 13 12
SWR
Reserved PEC POS ACK STOP
ST
Bit Name
15 SWRST
[14:13] Reserved
12 PEC
11 POS
V1.3
8
C=X +X
Table 13-1 I2C-related registers list
Offset address
0x40005400

I2C control register 1

0x40005404 I2C control register 2
0x40005408 I2C address register 1
0x4000540C I2C address register 2
0x40005410 I2C data register
0x40005414 I2C status register 1
0x40005418 I2C status register 2
0x4000541C I2C clock register
11 10 9 8
STAR
T
Access
Software reset, setting this bit by user code will
reset the I2C peripheral. Make sure the pins of the
I2C bus are released and the bus is idle before the
RW reset.
Note: This bit resets the I2C module when no stop
condition is detected on the bus but the busy bit is
1.
RO Reserved
Packet error checking bit, set this bit to enable
packet error detection. The user code can set or
clear this bit; the hardware clears this bit when the
PEC is transmitted, when a start or end signal is
RW generated, or when the PE bit is cleared to 0.
1: With PEC.
0: Without PEC.
Note: The PEC is invalidated when arbitration is
lost.
ACK and PEC position setting bits, which can be
RW
set or cleared by user code and can be cleared by
2
+X+1
Description
7 6 5
NOS
ENG ENPE
TRET
C C
CH
Description
150
http://wch.cn
Reset value
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
0x0000
4 3 2 1
Reserved
Reset value
0
0
0
0
0
PE