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WCH CH32L103 Reference Manual

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Overview
CH32L103 is an industrial-grade general-purpose microcontroller based on 32-bit RISC-V instruction set and
architecture. Adopting QingKe V4C core, it supports hardware interrupt stack and improves interrupt response
efficiency. This series of products are loaded with rich peripheral interfaces and functional modules. Its internal
organizational structure meets the low-cost and low-power embedded application scenarios.
This manual is aimed at user's application development and provides detailed information about the use of
CH32L103 products.
RISC-V core version comparison overview
Features
Instruction
Core
set
versions
QingKeV4B
IMAC
QingKeV4C
IMAC
QingKeV4F
IMAFC
Hardware
Interrupt
stack
nesting
interrupt
levels
levels
channels
2
2
2
2
3
8
CH32L103 Reference Manual
Fast
Integer
division
Vector table model
cycles
4
9
Address or command
4
5
Address or command
4
5
Address or command
V1.9
https://wch-ic.com
Extended
Memory
instruction
protection
Supported
None
Supported
Standard
Supported
Standard

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Summary of Contents for WCH CH32L103

  • Page 1 Overview CH32L103 is an industrial-grade general-purpose microcontroller based on 32-bit RISC-V instruction set and architecture. Adopting QingKe V4C core, it supports hardware interrupt stack and improves interrupt response efficiency. This series of products are loaded with rich peripheral interfaces and functional modules. Its internal organizational structure meets the low-cost and low-power embedded application scenarios.
  • Page 2 Abbreviated description of the bit attribute in the register: Register bit Property description attributes Read-only attribute, read a fixed value. Read-only attribute, changed by hardware. Read-only attribute, auto bit clear 0 after read operation. Write only attribute (not readable, read value uncertain) Write-only attribute, writable in Safe mode.

  • Page 3: Chapter 1 Memory And Bus Architecture

    CH32L103 Reference Manual https://wch-ic.com Chapter 1 Memory and Bus Architecture 1.1 Bus Architecture This series of products are general-purpose microcontrollers designed based on the RISC-V instruction set, and the core, arbitration unit, DMA module, SRAM storage and other parts of its architecture interact with each other through multiple sets of buses.
  • Page 4 CH32L103 Reference Manual https://wch-ic.com Figure 1-1 System block diagram : 1.8V~3.6V @VDD FLASH RISC-V (V4C) I-code Bus CTRL PFIC RV32 : 1.8V~3.6V SWCLK IMA(F)C @VDD D-code Bus SWDIO Flash Memory @VDDA DD A DMA Channels SRAM SYSCLK Reset & HBCLK PB1CLK MUX &...

  • Page 5: Memory Map

    1.2 Memory Map The CH32L103 family contains program memory, data memory, core registers, peripheral registers, and more, all addressed in a 4GB linear space. System storage stores data in small-end format, i.e., low bytes are stored at the low address and high bytes are stored at the high address.
  • Page 6 CH32L103 Reference Manual https://wch-ic.com Figure 1-2 Storage image USBFS 0x5000 0000 Reserved 0x4002 7400 USBPD 0x4002 7000 Reserved 0x4002 6400 OPA/CMP 0x4002 6000 Reserved 0x4002 3C00 EXTEN 0x4002 3800 Reserved 0x4002 3400 0x4002 3000 Reserved 0x4002 2400 Flash Interface 0x4002 2000...

  • Page 7: Memory Allocation

    CH32L103 Reference Manual https://wch-ic.com 1.2.1 Memory Allocation Built-in 20KB SRAM, starting address 0x20000000, supports byte, half-word (2 bytes), and full-word (4 bytes) access. Built-in up to 64KB program Flash memory (CodeFlash) for storing user applications. Built-in 3K+256B System memory (Bootloader) for storing the system bootloader (Factory-cured bootloader).

  • Page 8: Chapter 2 Power Control (Pwr)

    CH32L103 Reference Manual https://wch-ic.com Chapter 2 Power Control (PWR) 2.1 Overview The system operating voltage V ranges from 1.8 to 3.6 V. The built-in voltage regulator provides the low-voltage power supply required by the core. When the main power supply, V...

  • Page 9: Power Management

    CH32L103 Reference Manual https://wch-ic.com less than the reset lag time t and is more than 0.6V higher than the value of V , then there may be a short RSTTEMPO moment when the current is pumped into the V through the diode between the V...

  • Page 10: Low-Power Modes

    CH32L103 Reference Manual https://wch-ic.com Figure 2-3 Schematic diagram of PVD operation DD(A) Approx. 200mV Threshold value hysteresis output 2.3 Low-power Modes After a system reset, the microcontroller is in a normal operating state (run mode), where system power can be saved by reducing the system main frequency or turning off the unused peripheral clock or reducing the operating peripheral clock.
  • Page 11 CH32L103 Reference Manual https://wch-ic.com PDDS=0，LPDS=1 Stop mode RAMLV=1, PDDS=0，LPDS=1 WKUP pin rising edge, RTC alarm event, NRST pin reset, Set SLEEPDEEP IWDG reset, PVD's output. Disable HSE, to 1 Note: STANDBY HIS, PLL and Set PDDS to 1 EXTI0~EXTI17 external events...

  • Page 12: Standby Mode

    CH32L103 Reference Manual https://wch-ic.com (SLEEPDEEP) and allows the voltage regulator to operate in a much lower power consumption state. In this mode the high frequency clock (HSE/HSI/PLL) domain is switched off, the SRAM and register contents are maintained and the IO pin state is held. The system can continue to run after this mode wakes up and the HSI is called the default system clock.

  • Page 13: Register Description

    CH32L103 Reference Manual https://wch-ic.com Note: Putting the microprocessor into Stop or Standby mode in debug mode will lose the debug connection. R2KSTY=1 controls the address range of 2K byte RAM: 0x20000000-0x20000000+2K R18KSTY=1 controls the address range of 18K bytes of RAM: 0x20000000+2K-0x20000000+2K+18K 2.3.5 RTC Auto-wakeup...
  • Page 14 CH32L103 Reference Manual https://wch-ic.com VBAT is powered: 1: Powered; 0: Not powered. 2K RAM power switch control bit in Standby mode when R2KVBAT VBAT is powered: 1: Powered; 0: Not powered. Standby mode 18K RAM power switch control bit: R18KSTY 1: Powered;...
  • Page 15 CH32L103 Reference Manual https://wch-ic.com 011: Rising edge 2.35V/falling edge 2.28V; 100: Rising edge 2.54V/falling edge 2.46V; 101: Rising edge 2.72V/falling edge 2.63V; 110: Rising edge 2.92V/falling edge 2.83V; 111: Rising edge 3.10V/falling edge 3.01V. Power supply voltage monitoring function enable flag bit: PVDE 1: Enable power supply voltage monitoring function;...
  • Page 16 CH32L103 Reference Manual https://wch-ic.com in the PWR_CTLR register. 1: VDD and VDDA are below the PVD threshold set by PLS[2:0]; 0: VDD and VDDA are above the PVD threshold set by PLS[2:0]. Standby status flag bit, which can be cleared by CSBF position 1.

  • Page 17: Chapter 3 Reset And Clock Control (Rcc)

    CH32L103 Reference Manual https://wch-ic.com Chapter 3 Reset and Clock Control (RCC) The controller provides different forms of resets and configurable clock tree structures based on the division of power areas and peripheral power management considerations in the application. This section describes the scope of each clock in the system.

  • Page 18: Backup Domain Reset

    OPA reset: When the OPA reset is enabled, the high level of the OPA output will cause an OPA reset. USBPD Reset: When PD_RST_EN is 1, the CH32L103 supports the reset generated by the Hard Reset of the USBPD signal frame. If IE_RX_RESET is also 1, the Reset generated by Cable Reset of signal frames is also supported.
  • Page 19 CH32L103 Reference Manual https://wch-ic.com 3.3 Clock 3.3.1 System Clock Structure Figure 3-2 Clock tree block diagram ~40 KHz IWDGCLK to independent watchdog LSI RC to BKP 32.768 KHz OSC32_IN LSE OSC RTCCLK OSC32_ OUT to RTC /128 to OPA USBPRE USBFS /1,/1.5,/2,/2.5...
  • Page 20 CH32L103 Reference Manual https://wch-ic.com provide the system clock without any external devices. Its start-up time is very short, but the clock frequency accuracy is poor. The HSI is turned on and off by setting the HSION bit in the RCC_CTLR register, and the HSIRDY bit indicates whether the HSIRC oscillator is stable.
  • Page 21 CH32L103 Reference Manual https://wch-ic.com Figure 3-4 High-speed clock source circuit External clock HSE_ext source OSC_IN (Suspended) OSC_OUT 3.3.3 Low-speed Clock (LSI/LSE) LSI is a low-speed clock signal generated by a RC oscillator of about 40KHz in the system. It can be kept running in both downtime and standby modes, providing clock references for RTC clocks, independent watchdogs, and wake-up units.
  • Page 22 CH32L103 Reference Manual https://wch-ic.com 3.3.4 PLL Clock By configuring the RCC_CFGR0 register and the expansion register EXTEN_CTR, the internal PLL clock can choose three clock sources and frequency doubling factors, which must be set before each PLL is turned on, and these parameters cannot be changed once the PLL is started.
  • Page 23 CH32L103 Reference Manual https://wch-ic.com  LSE acts as the RTC clock: Since LSE is powered by V in the backup domain, RTC continues to work as long as V maintains power, even though V power is cut off.  LSI as the RTC clock: If the V power is cut off, RTC automatic wake up is not guaranteed.
  • Page 24 CH32L103 Reference Manual https://wch-ic.com If the current HSE is the system clock, or the current HSE is the PLL input clock and the PLL is the system clock, the clock security system will automatically switch the system clock to the HSI oscillator and turn off the HSE oscillator and PLL in the event of a HSE failure.
  • Page 25 CH32L103 Reference Manual https://wch-ic.com Clock security system enable: 1: Enable clock security system. When HSE is ready (HSERDY is set to 1), the hardware turns on the clock monitoring function for HSE and finds that HSE CSSON abnormal triggers the CSSF flag and NMI interrupt;...
  • Page 26 CH32L103 Reference Manual https://wch-ic.com Internal high-speed HSI stable ready flag (set by hardware) 1: Internal high-speed HSI is stable; HSIRDY 0 Internal high-speed HSI is not stable. Note: After the HSION bit is cleared, it needs 6 HSI cycles to clear 0.
  • Page 27 CH32L103 Reference Manual https://wch-ic.com 111: PLL clock output after 2 frequency division USB clock division frequency configuration: 00: 1-division frequency (for PLLCLK=48MHz); [23:22] USBPRE[1:0] 01: 2-division frequency (for PLLCLK=96MHz); 10: 1.5-division frequency (for PLLCLK=72MHz); 11: Reserved. PLL clock multiplication factor (not writable until PLL is off): 0000: PLL 2x output;...
  • Page 28 CH32L103 Reference Manual https://wch-ic.com HB clock source pre-divided control: 0xxx: SYSCLK no frequency division; 1000: SYSCLK 2-division frequency; 1001: SYSCLK 4-division frequency; 1010: SYSCLK 8-division frequency; [7:4] HPRE[3:0] 0000b 1011: SYSCLK 16-division frequency; 1100: SYSCLK 64-division frequency; 1101: SYSCLK 128-division frequency;...
  • Page 29 CH32L103 Reference Manual https://wch-ic.com 0: No effect. Clear HSE oscillator ready interrupt flag: HSERDYC 1: Clear HSERDYF interrupt flag; 0: No effect. Clear HSI oscillator ready interrupt flag: HSIRDYC 1: Clear HSIRDYF interrupt flag; 0: No effect. Clear LSE oscillator ready interrupt flag: LSERDYC 1: Clear LSERDYF interrupt flag;...
  • Page 30 CH32L103 Reference Manual https://wch-ic.com bit 1. HSI clock ready interrupt flag: 1: HSI clock ready generates an interrupt; HSIRDYF 0: No HSI clock ready interrupt. Set by hardware, clear when software write HSIRDYC bit 1. LSE clock ready interrupt flag: 1: LSE clock ready generates an interrupt;...
  • Page 31 CH32L103 Reference Manual https://wch-ic.com IO's PB port module reset control: IOPBRST 1: Reset module; 0: No effect. IO's PA port module reset control: IOPARST 1: Reset module; 0: No effect. Reserved Reserved I/O auxiliary function module reset control: AFIORST 1: Reset module; 0: No effect.
  • Page 32 CH32L103 Reference Manual https://wch-ic.com 1: Reset module; 0: No effect. [13:12] Reserved Reserved WWDG reset control: WWDGRST 1: Reset module; 0: No effect. [10:3] Reserved Reserved Timer 4 module reset control: TIM4RST 1: Reset module; 0: No effect. Timer 3 module reset control: TIM3RST 1: Reset module;...
  • Page 33 CH32L103 Reference Manual https://wch-ic.com Offset address: 0x18 Reserved USAR Reser Reser SPI1 TIM1 Reser IOPD IOPC IOPB IOPA Reser AFIO Reserved Name Access Description Reset value [31:15] Reserved Reserved USART1 interface clock enable: USART1EN 1: Module clock on; 0: Module clock off.
  • Page 34 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value LPTIM module clock enable: LPTIMEN 1: Module clock on; 0: Module clock off. [31:29] Reserved Reserved Power interface module clock enable: PWREN 1: Module clock on; 0: Module clock off. Backup unit clock enable: BKPEN 1: Module clock on;...
  • Page 35 CH32L103 Reference Manual https://wch-ic.com 3.4.9 Backup Domain Control Register (RCC_BDCTLR) Offset address: 0x20 Reserved RTCE LSEO Reserved RTCSEL[1:0] Reserved Name Access Description Reset value [31:17] Reserved Reserved Backup domain software reset control: BDRST 1: Reset the entire backup domain. 0: Undo the reset.
  • Page 36 CH32L103 Reference Manual https://wch-ic.com 1: Enable the LSE oscillator; 0: Disable the LSE oscillator. 3.4.10 Control/Status Register (RCC_RSTSCKR) Offset address: 0x24 Reser Reserved RSTF RSTF RSTF RSTF RSTF RSTF LSIO Reserved Name Access Description Reset value Low-power reset flag: 1: Occurrence of low-power resets.
  • Page 37 CH32L103 Reference Manual https://wch-ic.com Reserved Reserved Clear reset flag control: RMVF 1: Clear the reset flag. 0: No effect. [23:2] Reserved Reserved Internal low-speed clock (LSI) stabilization ready flag bit (set by hardware): 1: The internal low-speed clock (40KHz) is stabilized;...

  • Page 38: Chapter 4 Backup Register (Bkp)

    CH32L103 Reference Manual https://wch-ic.com Chapter 4 Backup Register (BKP) Backup register (BKP) provides 10 16-bit backup data registers that can be used to store 20 bytes of user data. After the main power supply (V ) is powered off, these data can still be maintained by V power supply, regardless of standby state, system reset or power reset.

  • Page 39: Rtc Calibration

    CH32L103 Reference Manual https://wch-ic.com Therefore, in order to prevent unnecessary tamper events, resulting in the removal of the backup register, it is recommended that when you want the hardware to detect the tamper pin, you should first clear the tamper event that the hardware may remember by writing the BKP_TPCSR register CTE position 1, and ensure that the current tamper detection pin state is invalid.
  • Page 40 CH32L103 Reference Manual https://wch-ic.com Offset address: 0x04-0x28 D[15:0] Name Access Description Reset value Backup data, can be called by the user program. Note: They are reset only by a Backup Domain [15:0] D[15:0] Reset (BDRST) or (if the Tamper Detection Pin TAMPER function is enabled) by an Tamper Pin Event.
  • Page 41 CH32L103 Reference Manual https://wch-ic.com calibrate the RTC clock, which can be slowed down from 0 to 121 ppm. 4.3.3 Tamper Detection Control Register (BKP_TPCTLR) Offset address: 0x30 Reserved TPAL TPE Name Access Description Reset value [15:2] Reserved Reserved Tamper detection pin (TEMPER pin) active level...
  • Page 42 CH32L103 Reference Manual https://wch-ic.com bit is not reset. [7:3] Reserved Reserved Tamper interrupt enable bit: 0: Disable tamper detection interrupt; 1: Enable tamper detection interrupt (TPE needs to be set to 1). TPIE Note 1: The tamper interrupt cannot wake up the core from low-power mode.

  • Page 43: Chapter 5 Cyclic Redundancy Check (Crc)

    CH32L103 Reference Manual https://wch-ic.com Chapter 5 Cyclic Redundancy Check (CRC) The cyclic redundancy check (CRC) computation unit is used to obtain the result of the CRC computation for any 32-bit data based on a fixed generating polynomial. It is generally used in the field of data storage and data communication to verify the correctness of data.
  • Page 44 CH32L103 Reference Manual https://wch-ic.com 5.3 Register Description Table 5-1 CRC-related registers list Name Access address Description Reset value R32_CRC_DATAR 0x40023000 Data register 0xFFFFFFFF R8_CRC_IDATAR 0x40023004 Independent data buffer 0x00 R32_CRC_CTLR 0x40023008 Control register 0x00000000 5.3.1 Data Register (CRC_DATAR) Offset address: 0x00...
  • Page 45 CH32L103 Reference Manual https://wch-ic.com execution, hardware auto clear, after execution, data register is 0xFFFFFFFF. V1.9...

  • Page 46: Chapter 6 Real Time Clock (Rtc)

    CH32L103 Reference Manual https://wch-ic.com Chapter 6 Real Time Clock (RTC) The Real Time Clock (RTC) is a standalone timer module with a programmable counter up to 32 bits, which can be used with software to realize the real time clock function, and the counter value can be modified to reconfigure the current time and date of the system.
  • Page 47 CH32L103 Reference Manual https://wch-ic.com be powered by VBAT. After inputting the frequency divider (RTC_DIV), the RTCCK is divided into TR_CLK. It is worth noting that the inside of the frequency divider (RTC_DIV) is a self-subtractive counter, which will output a TR_CLK from the overrun, then take the default value from the reload value register (RTC_PSCR) and reinstall it into the frequency divider, the read divider actually reads its real-time value (read only), and the write division factor should be written to the reload value register (RTC_PSCR).
  • Page 48 CH32L103 Reference Manual https://wch-ic.com 6.3.1 RTC Control Register High (RTC_CTLRH) Offset address: 0x00 ALRI SECI Reserved Name Access Description Reset value [15:3] Reserved Reserved OWIE RW Overflow interrupt enable. ALRIE RW Alarm interrupt enable. SECIE RW Second interrupt enable. 6.3.2 RTC Control Register Low (RTC_CTLRL)
  • Page 49 CH32L103 Reference Manual https://wch-ic.com first step should reset this bit. 1: The register is synchronized; 0: The register is not synchronized. Counter overflow flag, this bit is set by hardware when the 32-bit counter overflows. An overflow interrupt is also generated if the OWIE bit is set. This bit can only be cleared by software and cannot be set by software.
  • Page 50 CH32L103 Reference Manual https://wch-ic.com 6.3.5 Divider Register High (RTC_DIVH) Offset address: 0x10 Reserved DIV[19:16] Name Access Description Reset value [15:4] Reserved Reserved [3:0] DIV[19:16] Divider register high. 6.3.6 Divider Register Low (RTC_DIVL) Offset address: 0x14 DIV[15:0] Name Access Description Reset value Divider register low.
  • Page 51 CH32L103 Reference Manual https://wch-ic.com time by reading CNT [31:0]. To write this value, you need to enter configuration mode. 6.3.9 Alarm Register High (RTC_ALRMH) Offset address: 0x20 ALR[31:16] Name Access Description Reset value [15:0] ALR[31:16] WO Alarm register high xxxxh 6.3.10 Alarm Register Low (RTC_ALRML)

  • Page 52: Chapter 7 Independent Watchdog (Iwdg)

    CH32L103 Reference Manual https://wch-ic.com Chapter 7 Independent Watchdog (IWDG) The system is equipped with an independent watchdog (IWDG) to detect software failures caused by logic errors and external environment interference. The IWDG clock source comes from LSI and can be run independently of the main program, so it is suitable for situations with low precision requirements.
  • Page 53 CH32L103 Reference Manual https://wch-ic.com register indicates the update status of the frequency division value, and the frequency division value can only be modified and read out when the update is completed. 2) Reload value: used to update the current value of the counter in the independent watchdog, and the counter is decremented by this value.
  • Page 54 CH32L103 Reference Manual https://wch-ic.com 7.3.2 Prescaler Register (IWDG_PSCR) Offset address: 0x04 Reserved PR[2:0] Name Access Description Reset value [15:3] Reserved Reserved IWDG clock division factor, write 0x5555 to KEY before modifying this field. 000: Divided by 4; 001: Divided by 8;...
  • Page 55 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [15:2] Reserved Reserved The reinstall value updates the flag bit. Hardware setting or clearing 0. 1: Reload value update is in progress. 0: Reload update ends (up to 5 LSI cycles).

  • Page 56: Chapter 8 Window Watchdog (Wwdg)

    CH32L103 Reference Manual https://wch-ic.com Chapter 8 Window Watchdog (WWDG) The window watchdog is generally used to monitor the software failures of the system, such as external interference, unforeseen logic errors and so on. It needs to refresh the counter (feed the dog) within a specific window time (with upper and lower limits), otherwise the watchdog circuit will produce a system reset earlier or later than this window time.
  • Page 57 CH32L103 Reference Manual https://wch-ic.com  Watchdog configuration Inside the watchdog is a 7-bit counter running in a continuous cycle, which supports read and write access. To use the watchdog reset function, you need to perform the following actions: 1) Counter time base: The WDGTB[1:0] bits in the WWDG_CFGR register. Note to switch on the WWDG module clock of the RCC unit.
  • Page 58 CH32L103 Reference Manual https://wch-ic.com Note: The application program can write 0 to the T6-bit by software to implement system reset, which is equivalent to software reset function. 2) When the counter refresh action is executed when the feed dog operation is disabled, i.e., when write operation is performed on the T[6:0] bits when t ≤t≤t...
  • Page 59 CH32L103 Reference Manual https://wch-ic.com 8.3.2 WWDG Configuration Register (WWDG_CFGR) Offset address: 0x04 WDGTB[1:0 Reserved W[6:0] Name Access Description Reset value [15:10] Reserved Reserved Early wakeup interrupt: If it set to 1, interrupt is generated when the counter reaches 0x40. It can only be cleared by hardware after reset.

  • Page 60: Chapter 9 Interrupt And Events (Pfic)

    CH32L103 Reference Manual https://wch-ic.com Chapter 9 Interrupt and Events (PFIC) The built-in Programmable Fast Interrupt Controller (PFIC) supports up to 255interrupt vectors. The current system manages 51 peripheral interrupt channels and 4 core interrupt channels, and the rest are retained.
  • Page 61 CH32L103 Reference Manual https://wch-ic.com programmable TAMPER Tamper detection interrupt 0x00000048 programmable Real-time clock interrupt 0x0000004C programmable FLASH Flash global interrupt 0x00000050 programmable Reset and clock control interrupts 0x00000054 programmable EXTI0 EXTI line 0 interrupt 0x00000058 programmable EXTI1 EXTI line 1 interrupt...
  • Page 62 CH32L103 Reference Manual https://wch-ic.com LPTIM_WKU programmable LPTIM wakeup interrupt 0x000000E8 programmable USBFS USBFS global interrupt 0x000000EC USBFS_WKU programmable USBFS wakeup interrupt 0x000000F0 programmable USART4 USART4 global interrupt 0x000000F4 programmable DMA_CH8 DMA channel 8 global interrupt 0x000000F8 programmable LPTIM LPTIM global interrupt...
  • Page 63 CH32L103 Reference Manual https://wch-ic.com by the edge detection circuit. As long as one of the software interrupts or external interrupt signals is generated, it will be output to both event enabling and interrupt enabling circuits through the OR gate circuit in the diagram. As long as an interrupt is enabled or an event is enabled, an interrupt or event will occur.

  • Page 64: Exti Registers

    CH32L103 Reference Manual https://wch-ic.com configured by the AFIO_EXTICRx register. EXTI16 PVD event: Exceed the voltage detector threshold EXTI17 RTC alarm event EXTI19 USBPD wakeup event EXTI20 USBFS wakeup event EXTI21 LPTIM wakeup event EXTI22 COMP wakeup event 9.5 Register Description 9.5.1 EXTI Registers...
  • Page 65 CH32L103 Reference Manual https://wch-ic.com MR12 MR9 MR8 MR7 MR6 MR5 MR4 MR3 MR2 MR1 MR0 Name Access Description Reset value [31:23] Reserved Reserved Enable the event request signal for external interrupt channel x: [22:0] 1: Enable event for this channel;...
  • Page 66 CH32L103 Reference Manual https://wch-ic.com 9.5.1.5 Software Interrupt Event Register (EXTI_SWIEVR) Offset address: 0x10 SWIE SWIE SWIE SWIE Reser SWIE SWIE Reserved R 22 R 21 R 20 R 19 R 17 R 16 SWIE SWIE SWIE SWIE SWIE SWIE SWIE...

  • Page 67: Table Of Contents

    CH32L103 Reference Manual https://wch-ic.com PFIC interrupt priority threshold configuration R32_PFIC_ITHRESDR 0xE000E040 0x00000000 register R32_PFIC_CFGR 0xE000E048 PFIC interrupt configuration register 0x00000000 R32_PFIC_GISR 0xE000E04C PFIC interrupt global status register 0x00000000 R32_PFIC_VTFIDR 0xE000E050 PFIC VTF interrupt ID configuration register 0x00000000 R32_PFIC_VTFADDRR0 0xE000E060 PFIC VTF interrupt 0 address register...
  • Page 68 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value 16#-31#Interrupt current enable status. [31:16] INTENSTA 1: Current numbered interrupt is enabled; 0: Current numbered interrupt not enabled. Reserved Reserved 14# Interrupt current enable status. INTENSTA 1: Current numbered interrupt is enabled;...
  • Page 69 CH32L103 Reference Manual https://wch-ic.com INTENSTA Reser INTENSTA Reserved [68:67] [65:64] Name Access Description Reset value [31:5] Reserved Reserved 67#-68# Interrupt current enable status. [4:3] INTENSTA 1: Current numbered interrupt is enabled; 0: Current numbered interrupt not enabled. Reserved Reserved 64#-65# Interrupt current enable status.
  • Page 70 CH32L103 Reference Manual https://wch-ic.com PENDSTA[63:48] Reser PENDSTA[47:38] PENDSTA[36:32] Name Access Description Reset value 38#-63# interrupts currently pending status. 1: Current numbered interrupt is pending; [31:6] PENDSTA 0: Current numbered interrupt is not pending. Reserved Reserved 32#-36# interrupts currently pending status.

  • Page 71: Pfic Interrupt Configuration Register

    CH32L103 Reference Manual https://wch-ic.com Interrupt priority values lower than the current set value do not perform interrupt service when hung; a 0 in this register indicates that the threshold register function is invalid. [7:5]: Priority threshold value. [4:0]: Reserved, fixed to 0, write invalid.

  • Page 72: Pfic Vtf Interrupt Id Configuration Register

    CH32L103 Reference Manual https://wch-ic.com Whether an interrupt is currently pending: GPENDSTA 1: Yes; 0: No. Whether the interrupt is executed currently: GACTSTA 1: Yes; 0: No. Current interrupt nesting status, currently supports a maximum of 2 levels of nesting, with a maximum hardware stack depth of 2 levels.

  • Page 73: Pfic Vtf Interrupt 2 Address Register

    CH32L103 Reference Manual https://wch-ic.com Offset address: 0x64 ADDR1[31:16] VTF1E ADDR1[15:1] Name Access Description Reset value VTF interrupt 1 service program address [31:1] ADDR1 bit[31:1], bit0 is 0. VTF interrupt 1 enable bit: VTF1EN 1: Enabled VTF interrupt 1 channel; 0: Disabled.

  • Page 74: Pfic Interrupt Enable Set Register

    CH32L103 Reference Manual https://wch-ic.com 1: Enabled VTF interrupt 3 channel; 0: Disabled. 9.5.2.15 PFIC Interrupt Enable Set Register 1 (PFIC_IENR1) Offset address: 0x100 INTEN[31:16] Reser INTEN1 Reser INTEN1 Reserved Name Access Description Reset value 16#-31# interrupt enable control. [31:16] INTEN 1: Current numbered interrupt enable;...

  • Page 75: Pfic Interrupt Enable Set Register

    CH32L103 Reference Manual https://wch-ic.com 9.5.2.17 PFIC Interrupt Enable Set Register 3 (PFIC_IENR3) Offset address: 0x108 Reserved INTEN Reserve INTEN Reserved [68:67] [65:64] Name Access Description Reset value [31:5] Reserved Reserved 67#-68# interrupt enable control. [4:3] INTEN 1: Current numbered interrupt enable;...

  • Page 76: Pfic Interrupt Enable Clear Register

    CH32L103 Reference Manual https://wch-ic.com INTRSET[63:48] Reser INTRSET[47:38] INTRSET[36:32] Name Access Description Reset value 38#-63# interrupt shutdown control. [31:6] INTRSET 1: Current numbered interrupt shutdown; 0: No effect. Reserved Reserved 32#-36# interrupt shutdown control. [4:0] INTRSET 1: Current numbered interrupt shutdown;...

  • Page 77: Pfic Interrupt Pending Set Register

    CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value 16#-31# interrupt pending settings. [31:12] PENDSET 1: Current numbered interrupt pending; 0: No effect. Reserved Reserved 14# interrupt pending settings, 13# and 15# reserved. PENDSET 1: Current numbered interrupt pending; 0: No effect.

  • Page 78: Pfic Interrupt Pending Clear Register

    CH32L103 Reference Manual https://wch-ic.com Reserved PENDSET[68:64] Name Access Description Reset value [31:5] Reserved Reserved 64#-68# interrupt pending settings. [4:0] PENDSET 1: Current numbered interrupt pending; 0: No effect. 9.5.2.24 PFIC Interrupt Pending Clear Register 1 (PFIC_IPRR1) Offset address: 0x280 PENDRST[31:16]...

  • Page 79: Pfic Interrupt Pending Clear Register

    CH32L103 Reference Manual https://wch-ic.com PENDRST[63:48] Reser PENDRST[47:38] PENDRST[36:32] Name Access Description Reset value 38#-63# interrupt pending clear. 1: Current numbered interrupt clears the [31:6] PENDRST pending state; 0: No effect. Reserved Reserved 32#-36# interrupt pending clear. 1: Current numbered interrupt clears the...

  • Page 80: Pfic Interrupt Activation Register

    CH32L103 Reference Manual https://wch-ic.com Reser IACTS1 Reser IACTS1 IACTS IACTS Reserved Reserved Name Access Description Reset value 16#-31# interrupt execution status. [31:16] IACTS 1: Current numbered interrupt is executing; 0: Current numbered interrupt not executed. Reserved Reserved 14# interrupt execution status.

  • Page 81: Pfic Interrupt Priority Configuration Register

    CH32L103 Reference Manual https://wch-ic.com Reserved IACTS Reser IACTS Reserved [68:67] [65:64] Name Access Description Reset value [31:5] Reserved Reserved 67#-68# interrupt execution status. [4:3] IACTS 1: Current numbered interrupt is executing; 0: Current numbered interrupt not executed. Reserved Reserved 64#-65# interrupt execution status.

  • Page 82: Pfic System Control Register

    CH32L103 Reference Manual https://wch-ic.com [4:0]: Reserved, fixed to 0, write invalid. 9.5.2.31 PFIC System Control Register (PFIC_SCTLR) Offset address: 0xD10 Reserved WFIT SLEE SLEEP LOCK Reser Reserved ONPE ONEX DEEP Name Access Description Reset value System reset, auto clear 0. Write 1 is valid,...
  • Page 83 CH32L103 Reference Manual https://wch-ic.com 1: The system enters low-power mode; 0: The system enters the main program. Reserved Reserved 9.5.3 Dedicated CSR Registers Some control and status registers (CSR) are defined in the RISC-V architecture to configure or identify or record the running status.
  • Page 84 CH32L103 Reference Manual https://wch-ic.com 19 18 BASEADDR[31:16] MODE BASEADDR[15:2] Name Access Description Reset value [31:2] BASEADDR[31:2] Interrupt vector table base address. Interrupt vector table recognition mode: 0: Recognized by jump instruction, limited MODE1 range, supports non-jump instructions; 1: Recognized by absolute address, full range supported, but must jump.
  • Page 85 CH32L103 Reference Manual https://wch-ic.com Name Description Lock enable, unlockable machine mode 0: Not locked; 1: Lock the related registers. [6:5] Reserved [7:0] pmp0cfg Address alignment and protected [4:3] area range selection. Executable attributes. Writable attributes. Readable attributes. For address aligned and protection region range selection, it performs memory protection for the region between A_ADDR and B_ADDR (A_ADDR and B_ADDR are both required 4-byte aligned): 1.
  • Page 86 CH32L103 Reference Manual https://wch-ic.com 9.5.4.3 PMP Address 1 Register (PMPADDR1) CSR address: 0x3B1 19 18 ADDR1[33:18] ADDR1[17:2] Name Access Description Reset value PMP set bit[33:2] of address 1, actual high 2 bits [31:0] ADDR1 unused. 9.5.4.4 PMP Address 2 Register (PMPADDR2)
  • Page 87 CH32L103 Reference Manual https://wch-ic.com R32_STK_CNTH 0xE000F00C System counter high register 0x00000000 R32_STK_CMPLR 0xE000F010 Count/compare low register 0x00000000 R32_STK_CMPHR 0xE000F014 Count/compare high register 0x00000000 Note: Applied for general-purpose MCUs designed based on 32-bit RISC-V instruction set and architecture. 9.5.5.1 System Count Control Register (STK_CTLR)
  • Page 88 CH32L103 Reference Manual https://wch-ic.com 1: Starts the system counter STK; 0: Turn off the system counter STK and the counter stops counting. 9.5.5.2 System Count Status Register (STK_SR) Offset address: 0x04 Reserved CNTI Reserved Name Access Description Reset value [31:1]...
  • Page 89 CH32L103 Reference Manual https://wch-ic.com 9.5.5.5 Count/Compare Low Register (STK_CMPLR) Offset address: 0x10 CMP[31:16] CMP[15:0] Name Access Description Reset value [31:0] CMP[31:0] RW Set the low 32 bits of the compare counter value. Note: Register STK_CMPLR and register STK_CMPHR together form the 64-bit counter comparison value.

  • Page 90: Chapter 10 Gpio And Alternate Functions (Gpio/Afio)

    CH32L103 Reference Manual https://wch-ic.com Chapter 10 GPIO and Alternate Functions (GPIO/AFIO) The GPIO ports can be configured for multiple input or output modes, have built-in shutdown pull-up or pull-down resistors, and can be configured for push-pull or open-drain functions. The GPIO ports can also be multiplexed for other functions.

  • Page 91: Function Description

    CH32L103 Reference Manual https://wch-ic.com 10.2 Function Description 10.2.1 Overview Figure 10-1 Basic structure of GPIO module Analog Input To on-chip peripheral Alternate Function Input on/off on/off on/off Input data Read register TTL Schmitt Protection trigger diode on/off Input driver I/O pin...

  • Page 92: Locking Mechanism

    CH32L103 Reference Manual https://wch-ic.com  Using the alternate function in the output direction, the port must be configured in the alternate output mode, and push-pull or open-drain can be set according to the actual situation.  For two-way alternate, the port must be configured in multiplexed output mode, when the driver is configured in floating input mode.

  • Page 93: Output Configuration

    CH32L103 Reference Manual https://wch-ic.com 10.2.7 Output Configuration Figure 10-3 Output configuration structure block diagram of GPIO module Input data Read register TTL Schmitt Protection trigger diode Input driver I/O pin Write Bit set/reset registers Output driver Protection diode P-MOS Output...

  • Page 94: Analog Input Configuration

    CH32L103 Reference Manual https://wch-ic.com 10.2.9 Analog Input Configuration Figure 10-5 Configuration structure block diagram of GPIO module as analog input To on-chip Analog Input peripheral Input data Read register TTL Schmitt Protection trigger diode Input driver I/O pin Bit set/reset...
  • Page 95 CH32L103 Reference Manual https://wch-ic.com USARTx_RTS Hardware flow control Push-pull alternate output USARTx_CTS Hardware flow control Floating input or pull-up input Table 10-4 Serial Peripheral Interface (SPI) module SPI pin Configuration GPIO configuration Master mode Push-pull alternate output SPIx_SCK Slave mode...
  • Page 96 CH32L103 Reference Manual https://wch-ic.com Table 10-9 Other IO function settings Pinout Configuration function GPIO configuration RTC output TAMPER_RTC Hardware automatic setting Tamper event input Clock output Push-pull alternate output Floating input or pull-up or pull- EXTI External interrupt input down input...
  • Page 97 CH32L103 Reference Manual https://wch-ic.com TIM2_CH3 PB10 PB10 PB12 PB12 TIM2_CH4 PB11 PB11 Table 10-13 TIM3 alternate function remapping Alternate function TIM3_CH1 TIM3_CH2 TIM3_CH3 TIM3_CH4 Table 10-14 TIM4 alternate function remapping Alternate function TIM4_CH1 PB10 TIM4_CH2 PB11 TIM4_CH3 TIM4_CH4 Table 10-15 LPTIM alternate function remapping...
  • Page 98 CH32L103 Reference Manual https://wch-ic.com Table 10-18 USART3 alternate function remapping Alternate function USART3_TX PB10 USART3_RX PB11 USART3_CK PB12 PB12 PB12 USART3_CTS PB13 PB13 PB13 USART3_RTS PB14 PB14 PB14 Table 10-19 USART4 alternate function remapping Alternate function USART4_TX USART4_RX USART4_CK USART4_CTS...

  • Page 99: Register Description

    CH32L103 Reference Manual https://wch-ic.com voltage output. Setting RB_UC_RST_SIE=0 turns on USB, setting RB_UH_PD_DIS=0 in R8_UHOST_CTRL enables the internal 15K pull-down, and setting BC_VSRC=1 for UDM/UDP enables the BC protocol source voltage VBC_SRC output. Setting UDM/UDP's BC_CMPE=1 enables the BC protocol comparator; a read operation of UDM/UDP's BC_CMPO bit acquires the state of the pin voltage compared with the BC protocol reference VBC_REF.
  • Page 100 CH32L103 Reference Manual https://wch-ic.com R32_GPIOB_LCKR 0x40010C18 PB port lock configuration register 0x00000000 R32_GPIOC_LCKR 0x40011018 PC port lock configuration register 0x00000000 R32_GPIOD_LCKR 0x40011418 PD port lock configuration register 0x00000000 10.3.1.1 GPIO Configuration Register Low (GPIOx_CFGLR) (x=A/B/C/D) Offset address: 0x00 MODE6[1:0 MODE5[1:0...
  • Page 101 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value (y=8-15), the configuration bits for port x, by which the corresponding port is configured. [31:30] When in input mode (MODE=00b): [27:26] 00: Analog input mode; [23:22] 01: Float input mode; [19:18] 10: With pull-up and pull-down modes.
  • Page 102 CH32L103 Reference Manual https://wch-ic.com ODR1 ODR1 ODR1 ODR1 ODR1 ODR1 ODR9 ODR8 ODR7 ODR6 ODR5 ODR4 ODR3 ODR2 ODR1 ODR0 Name Access Description Reset value [31:16] Reserved Reserved For output mode: (y=0-15). the port outputs data. This data can only be manipulated in 16-bit form.
  • Page 103 CH32L103 Reference Manual https://wch-ic.com effect. These bits can only be accessed in 16-bit form. 10.3.1.7 Configuration Lock Register (GPIOx_LCKR) (x=A/B/C/D) Offset address: 0x18 Reserved LCKK LCK1 LCK1 LCK1 LCK1 LCK1 LCK1 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0...
  • Page 104 CH32L103 Reference Manual https://wch-ic.com R32_AFIO_EXTICR4 0x40010014 External interrupt configuration register 4 0x00000000 R32_AFIO_CR 0x40010018 Control register 0x00000000 R32_AFIO_PCFR2 0x4001001C Remap register 2 0x00000000 10.3.2.1 Event Control Register (AFIO_ECR) Offset address: 0x00 Reserved Reserved PORT[2:0] PIN[3:0] Name Access Description Reset value...

  • Page 105: Default Mapping

    CH32L103 Reference Manual https://wch-ic.com 0xx: Enable SDI; 100: Disable SDI as a GPIO function; Other: Invalid. [23:16] Reserved Reserved Pin PD0&PD1 remap bit, which can be read or written by the user. It controls whether the GPIO functions of PD0 & PD1 are remapped, i.e. PD0 &...
  • Page 106 CH32L103 Reference Manual https://wch-ic.com CH3/PA2, CH4/PA3); 010: Partial mapping (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11); 011: Full mapping (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11); 100: Complete mapping (CH1/ETR/PA3, CH2/PA2, CH3/PB12, CH4/PA6); 101: Complete mapping (CH1/ETR/PA12, CH2/PA2, CH3/PB12, CH4/PA6); 111: Complete mapping (CH1/ETR/PA12, CH2/PB8, CH3/PA5, CH4/PA4).
  • Page 107 CH32L103 Reference Manual https://wch-ic.com 10: Partial remapping (TX/PD1, RX/PD0, CK/PB12, CTS/PB13, RTS/PB14) 11: Partial remapping (TX/PD0, RX/PD1, CK/PB12, CTS/PB13, RTS/PB14) The remap bit of USART2, combined with the USART2_RM_H field of remap register 2, {USART2_RM_H,USART2_RM}. This bit can be read and written by the user. It controls the...
  • Page 108 CH32L103 Reference Manual https://wch-ic.com 10: Full mapping (SCL/PA13, SDA/PA12) 11: Full mapping (SCL/PB9, SDA/PB11) The remap of SPI1 is combined with the SPI1_RM_H field remap register {SPI1_RM_H, SPI1_RM}. This bit can be read or written by the user. It controls the mapping of...
  • Page 109 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [31:16] Reserved Reserved (x=4-7), external interrupt input pin configuration bit. Used to determine which port pin the external [15:12] interrupt pin is mapped to: [11:8] 0000: xth pin of the PA pin;...
  • Page 110 CH32L103 Reference Manual https://wch-ic.com 0001: xth pin of the PB pin; 0010: xth pin of the PC pin; 0011: xth pin of the PD pin; Other: Reserved. 10.3.2.7 Control Register (AFIO_CR) Offset address: 0x18 UDM_ UDP_ UDP_ UDP_ _BC_ Reserved...
  • Page 111 CH32L103 Reference Manual https://wch-ic.com reduces power consumption during communication; 0: Normal GPIO threshold input. [8:0] Reserved Reserved 10.3.2.8 Remap Register 2 (AFIO_PCFR2) Offset address: 0x1C USAR I2C1_ TIM1_ LPTIM SPI1_ TIM2_ USART1 Reser Reserved T2_R RT4_ RM_H RM_H _RM_H RM_H...
  • Page 112 CH32L103 Reference Manual https://wch-ic.com (BKIN) of Timer 1 on the GPIO port: 000: Default mapping (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) 001: Fully mapped (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) 010: Fully mapping (ETR/PB6, CH1/PA1, CH2/PA7,...
  • Page 113 CH32L103 Reference Manual https://wch-ic.com GPIO port: 000: Default mapping (TX/PA9, RX/PA10, CK/PA8, CTS/PA11, RTS/PA12) 001: Fully mapping (TX/PB6, RX/PB7, CK/PA8, CTS/PA11, RTS/PA12) 010: Fully mapped (TX/PA4, RX/PA5, CK/PA3, CTS/PA2, RTS/PA13) 011: Fully mapped (TX/PA5, RX/PA4, CK/PA6, CTS/PB7, RTS/PB8) 100: Fully mapped (TX/PB11, RX/PB9, CK/PA6,...

  • Page 114: Chapter 11 Direct Memory Access Control (Dma)

    CH32L103 Reference Manual https://wch-ic.com Chapter 11 Direct Memory Access Control (DMA) Direct Memory Access (DMA) controllers provide a high-speed means of transferring data between a peripheral and memory or between memory and memory without CPU intervention, and data can be moved quickly through the DMA to conserve CPU resources for other operations.
  • Page 115 CH32L103 Reference Manual https://wch-ic.com address specified in the DMA_PADDRx or DMA_MADDRx register. 3) perform a decrement operation of the values in the DMA_CNTRx register, which indicates the current number of outstanding operations. Each channel has 3 DMA data transfer modes: ...
  • Page 116 CH32L103 Reference Manual https://wch-ic.com occurred, and the channel is closed. If TEIE is set in the DMA_CFGRx register, an interrupt will occur. When querying the status of the DMA channel, the application can first access the GIFx bit of the DMA_INTFR register, determine which channel has the DMA event, and then deal with the specific DAM event content of the channel.
  • Page 117 CH32L103 Reference Manual https://wch-ic.com 0x06/B7B6 0x0C/0000B7B6 0x00/B3B2 B1B0 0x04/B7B6 0x00/B0 B5B4 0x01/B4 0x08/BBBA 0x02/B8 B9B8 0x03/BC 0x0C/BFBE BDBC 0x00/B3B2 B1B0 0x04/B7B6 0x00/B1B0 B5B4 0x02/B5B4 0x08/BBBA 0x04/B9B8 B9B8 0x06/BDBC 0x0C/BFBE BDBC 0x00/B3B2 B1B0 0x04/B7B6 0x00/B3B2B1B0 B5B4 0x04/B7B6B5B4 0x08/BBBA 0x08/BBBAB9B8 B9B8 0x0C/BFBEBDBC...

  • Page 118: Dma Request Mapping

    CH32L103 Reference Manual https://wch-ic.com 11.2.3 DMA Request Mapping Figure 11-1 DMA request mapping EN bit o f chann el 1 USART4_TX Hardware request1 TIM2_CH3 Channel 1 TIM4_CH1 Software Trigger Arbiter MEM2MEM bit SPI1_RX EN bit o f chann el 2...

  • Page 119: Register Description

    CH32L103 Reference Manual https://wch-ic.com USART2_R USART2_T USART2 USART3_T USART3_R USART3 USART4_T USART4_R USART4 I2C1 I2C1_TX I2C1_RX I2C2 I2C2_TX I2C2_RX TIM1_CH4 TIM1_TRI TIM1 TIM1_CH1 TIM1_CH2 TIM1_UP TIM1_CH3 TIM1_CO TIM2 TIM2_CH3 TIM2_UP TIM2_CH1 TIM2_CH2 TIM2_CH4 TIM3_CH1 TIM3_CH4 TIM3 TIM3_CH3 TIM3_TRI TIM3_UP TIM4...
  • Page 120 CH32L103 Reference Manual https://wch-ic.com R32_DMA_PADDR5 0x40020060 DMA channel 5 peripheral address register 0x00000000 R32_DMA_MADDR5 0x40020064 DMA channel 5 memory address register 0x00000000 R32_DMA_CFGR6 0x4002006C DMA channel 6 configuration register 0x00000000 R32_DMA_CNTR6 0x40020070 DMA channel 6 transfer data number register 0x00000000...
  • Page 121 CH32L103 Reference Manual https://wch-ic.com this flag. Global interrupt flag for channel x (x=1/2/3/4/5/6/7/8): 1: TEIFx or HTIFx or TCIFx was generated on channel x; 28/24/20/16 0: No TEIFx or HTIFx or TCIFx has been generated on GIFx /12/8/4/0 channel x.
  • Page 122 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [31:15] Reserved Reserved Memory to memory mode enable: MEM2MEM 1: Enable memory to memory mode; 0: Disable memory to memory mode. Channel priority level setting: [13:12] PL[1:0] 00: Low; 01: Medium;...
  • Page 123 CH32L103 Reference Manual https://wch-ic.com Reserved NDT[15:0] Name Access Description Reset value [31:16] Reserved Reserved Number of data transfers, range 0-65535. Indicating the remaining number of transfers (the register contents are decremented after each DMA transfer). [15:0] NDT[15:0] When the channel is in loop mode, the contents of the register are automatically reloaded to the previously configured value.
  • Page 124 CH32L103 Reference Manual https://wch-ic.com automatically aligns with 2 bytes; when MSIZE [1:0] =' 10'(32 bits), the module automatically ignores bit [1:0], and the operation address automatically aligns with 4 bytes. Note: This register can only be changed when EN=0, and cannot be written when EN=1.

  • Page 125: Chapter 12 Analog-To-Digital Converter (Adc)

    CH32L103 Reference Manual https://wch-ic.com Chapter 12 Analog-to-digital Converter (ADC) The ADC module contains a 12-bit successive approximation analog-to-digital converter with the highest 48MHz input clock. Support 10 external channels and 3 internal signal source sampling sources. It can complete the functions of single conversion, continuous conversion, automatic scanning mode, discontinuous mode, external trigger mode and so on.

  • Page 126: Module Structure

    CH32L103 Reference Manual https://wch-ic.com 12.2 Functional Description 12.2.1 Module Structure Figure 12-1 ADC module block diagram Rule channel data Conversion ends EOC=1 register (16 bits) End of Injection Injection channel data conversion JEOC=1 register (4×16 bits) -ADC_IOFRx[11:0] ADC_IN0 0 Analog to...
  • Page 127 CH32L103 Reference Manual https://wch-ic.com 2) Sample clock The register operation of the module is based on the PCLK2 (PB2 bus) clock. The clock reference ADCCLK of the conversion unit is synchronized with the PCLK2. The frequency division is configured by the ADCPRE [1:0] domain of the RCC_CFGR0 register, and the maximum cannot exceed 48MHz.
  • Page 128 CH32L103 Reference Manual https://wch-ic.com = Sampling time + 12.5T CONV ADCCLK The sampling time can be determined according to SMPx [2:0] SMPx[2:0] Sample time (ADC_LP=0) Sample time (ADC_LP=1) 1.5 cycles 7.5 cycles 7.5 cycles 11.5 cycles 13.5 cycles 17.5 cycles 28.5 cycles...
  • Page 129 CH32L103 Reference Manual https://wch-ic.com 4ns to get an ADC clock with a duty cycle of about 75%. When set to 0, the input clock is not processed. The FIFO_EN bit enables ADCFIFO at high levels. ADC_LP bit controls ADC low power mode, vcmbuffer and comparator have high power consumption when set 1, which is suitable for sampling rate of 1m and above, and enter low power mode when setting 0.
  • Page 130 CH32L103 Reference Manual https://wch-ic.com ADON bit set Single channel mode: A regular channel to 1 performs a single conversion. Single channel mode: A regular channel or a External channel of an injection channel performs a trigger mode single conversion. Single scan mode: performs a single...
  • Page 131 CH32L103 Reference Manual https://wch-ic.com repeat a new round of conversion at the end external of each round until the CONT is cleared 0. trigger mode Note: The external trigger events of the rule group and the injection group are different, and the 'ADON' bit can only start the rule group channel transformation, so the start events of the rule group and injection group channel transformation are independent.
  • Page 132 CH32L103 Reference Manual https://wch-ic.com Note: When the ADC clock pre-division factor (ADCPRE [1:0]) is 4 to 8, 1 ADCCLK interval is automatically inserted when switching from regular conversion to injection sequence or from injection conversion to regular sequence; when the ADC clock pre-division factor is 2, there is a delay of 2 ADCCLK intervals.
  • Page 133 CH32L103 Reference Manual https://wch-ic.com conversion flag JEOC is set, and an interrupt is generated if JEOCIE is set. 12.2.5 Analog Watchdog If the analog voltage being converted by the ADC is below the low threshold or above the high threshold, the AWD analog watchdog status bit is set.

  • Page 134: Register Description

    CH32L103 Reference Manual https://wch-ic.com is more suitable for detecting the change of temperature rather than measuring the absolute temperature. If you need to measure the temperature accurately, you should use an external temperature sensor. By setting the TSVREFE position 1 of the ADC_CTLR2 register, awakening the ADC internal sampling channel, software startup or external trigger starts the temperature sensor channel conversion of the ADC, and reads the data result (mV).
  • Page 135 CH32L103 Reference Manual https://wch-ic.com Reserved JSTR Reserved STRT JEOC EOC AWD Name Access Description Reset value [31:5] Reserved Reserved Regular channel conversion start status: 1: The regular channel conversion has started; STRT 0: The regular channel conversion has not started.
  • Page 136 CH32L103 Reference Manual https://wch-ic.com JDISC DISC JAUT JEOC DISCNUM[2:0] SCAN AWDIE AWDCH[4:0] Name Access Description Reset value [31:29] Reserved Reserved ADC channel gain configuration: 00: x1 01: x4 10: x16 [28:27] PGA[1:0] 11: x64 Note: The input gain can be configured, for amplifying small signals and sampling.
  • Page 137 CH32L103 Reference Manual https://wch-ic.com 1: Enable automatic injection channel group conversion. 0: Disable automatic injection channel group conversion. Note: This mode needs to disable the external trigger function of the injection channel. In scan mode, analog watchdog enable bit on a single...
  • Page 138 CH32L103 Reference Manual https://wch-ic.com 12.3.3 ADC Control Register 2 (ADC_CTLR2) Offset address: 0x08 Reser Reserved STAR STAR EXTSEL[2:0] TRIG JEXT ALIG JEXTSEL[2:0] Reserved Reserved TRIG Name Access Description Reset value [31:24] Reserved Reserved Temperature sensor and internal voltage (V REFINT...
  • Page 139 CH32L103 Reference Manual https://wch-ic.com 1: Enable conversion on external event; 0: Disable conversion on external event. External trigger event select for injected channels: 000: TRGO event of timer 1; 001: CC4 event of timer 1; 010: TRGO event of timer 2;...
  • Page 140 CH32L103 Reference Manual https://wch-ic.com 12.3.4 ADC Sample Time Configuration Register 1 (ADC_SAMPTR1) Offset address: 0x0C 30 29 Reserved SMP18[2:0] SMP17[2:0] SMP16[2:0] Reserved 14 13 Reserved Name Access Description Reset value [31:27] Reserved Reserved SMPx[2:0]: Sample time configuration of channel x: 000: 1.5 cycles;...
  • Page 141 CH32L103 Reference Manual https://wch-ic.com SMPx [2:0]: sampling time configuration for channel x (ADC_LP=1): 000: 1.5 cycles; 001: 7.5 cycles; 010: 13.5 cycles; 011: 28.5 cycles; 100: 41.5 cycles; 101: 55.5 cycles; 110: 71.5 cycles; 111: 239.5 cycles; These bits are used to select the sampling time of each channel independently, and the channel configuration value must remain unchanged during the sampling period.
  • Page 142 CH32L103 Reference Manual https://wch-ic.com 14 13 Reserved LT[11:0] Name Access Description Reset value [31:12] Reserved Reserved [11:0] LT[11:0] RW Analog watchdog low threshold set bits. Note: The values of WDHTR and LTR can be changed during the conversion, but they will take effect in the next conversion.
  • Page 143 CH32L103 Reference Manual https://wch-ic.com Number of the 11th conversion channel in the regular [24:20] SQ11[4:0] sequence (0-9, 16-18). Number of the 10th conversion channel in the regular [19:15] SQ10[4:0] sequence (0-9, 16-18). Number of the 9th conversion channel in the regular...
  • Page 144 CH32L103 Reference Manual https://wch-ic.com Injects the number of channels to be converted in the [21:20] JL[1:0] channel conversion sequence: 00-11: 1-4 conversions. Inject the number of the 4th conversion channel in the sequence (0-9, 16-18). [19:15] JSQ4[4:0] Note: The software writes and assigns the channel number (0-9, 16-17) as the 4th in the sequence to be converted.
  • Page 145 CH32L103 Reference Manual https://wch-ic.com DATA Name Access Description Reset value [31:16] Reserved Reserved Regular channel converted data (data left alignment or [15:0] DATA right alignment). 12.3.15 ADC Configuration Register (ADC_CFG) Offset address: 0x50 TKEY_DRV_OUT Reserved FIFO TKEY_DRV_OUTEN RST_ ADC_BUFTRIM RV_E...
  • Page 146 CH32L103 Reference Manual https://wch-ic.com V1.9...

  • Page 147: Chapter 13 Touch Key Detection (Tkey)

    CH32L103 Reference Manual https://wch-ic.com Chapter 13 Touch Key Detection (TKEY) The touch detection control (TKEY) unit, with the help of the voltage conversion function of the ADC module, realizes the touch key detection function by converting the capacitance to the voltage for sampling. The detection channel reuses 10 external channels of the ADC, and the touch key detection is realized through the single conversion mode of the ADC module.
  • Page 148 CH32L103 Reference Manual https://wch-ic.com 13.2 TKEY Operations Steps TKEY detection belongs to the expansion function of ADC module, and its working principle is to change the capacitance perceived by hardware channel through "touch" and "non-touch" mode, and then convert the change of capacitance into voltage change through the number of charge and discharge cycles that can be set, and finally convert it into digital value through ADC module.
  • Page 149 CH32L103 Reference Manual https://wch-ic.com Total charge time TCHG = TKCGOFFSET + SMPx Note: This register maps the injected data register1 (ADC_IDATAR1) of the ADC module. So when write operation is performed on this address register, it serves as TKEY charge time offset (TKEY_ CHGOFFSET). When read operation is performed, it serves as the injected data register1 (ADC_IDATAR1) of the ADC module.

  • Page 150: Chapter 14 Advanced-Control Timer (Adtm)

    CH32L103 Reference Manual https://wch-ic.com Chapter 14 Advanced-control Timer (ADTM) The advanced-control timer module contains a powerful 16-bit automatic reset timer (TIM1), which can be used to measure pulse width or generate pulses, PWM waves, etc. Used in motor control, power supply and other fields.
  • Page 151 CH32L103 Reference Manual https://wch-ic.com provide a clock for the core counter CNT. Each compare/capture channel has a set of compare/capture register (CHxCVR), which supports comparison with the main counter (CNT) so as to output pulse. Figure 14-1 Structure block diagram of advanced-control timer...

  • Page 152: Clock Input

    CH32L103 Reference Manual https://wch-ic.com 14.2.2 Clock Input Figure 14-2 CK_PSC source block diagram of advanced-control timer TIMx_SMCR TS[2:0] ITRx TI1_ED TI2F TI1F Encoder TI1FP1 TI2F_Rising mode TI2FP2 Edge Filter detector TI2F_Falling ETRF TRGI External clock mode 1 CC2P ICF[3:0] CK_PSC...
  • Page 153 CH32L103 Reference Manual https://wch-ic.com 14.2.2.3 External Clock Source Mode 2 Use external trigger mode 2 to count on every rising or falling edge of the external clock pin input. When the ECE bit is set, the external clock source mode 2 is used. When the external clock source mode2 is used, ETRF is selected as CK_PSC.
  • Page 154 CH32L103 Reference Manual https://wch-ic.com Figure 14-3 Structure block diagram of compare/capture channel TI1F_ED To the slave mode controller TI1F_Rising TI1F TI1FP1 Filter Edge TI1F_Falling downcounter detector Divider TI2FP1 /1,/2,/4,/8 ICF[3:0] CC1P/CC1NP TIMx_CCMR1 TIMx_CCER (from slave mode controller) TI2F_Rising (from channel 2)
  • Page 155 CH32L103 Reference Manual https://wch-ic.com TI1FP1 and TI2FP1 from channel 2 are sent to CC1S together to be selected as IC1, and then sent to the compare/capture register after going through the ICPS frequency division. The compare/capture register is composed of a preload register and a shadow register, and only the preload register is operated during reading and writing.
  • Page 156 CH32L103 Reference Manual https://wch-ic.com If a repeat counter is used, an update event (UEV) is generated when the number of repetitions of the decrement count reaches the number of times programmed in the repeat counter register (R16_TIMx_RPTCR+1). Otherwise, an update event is generated each time the counter is overflowed.

  • Page 157: Input Capture Mode

    CH32L103 Reference Manual https://wch-ic.com In addition, if the URS bit (Update request selection) in the R16_TIMx_CTLR1 register is set to 1, setting the UG location 1 generates a UEV update event, but the UIF flag is not set to 1 (Therefore, no interrupts or DMA requests are sent).

  • Page 158: Forced Output Mode

    CH32L103 Reference Manual https://wch-ic.com compare/capture register. OCxM (in R16_TIMx_CHCTLRx) and the CCxP bit (in R16_TIMx_CCER) determine whether the output is determined high or low level or level inversion. When a comparison consistent event is generated, the CCxIF bit will be also set. If the CCxIE bit is preset, an interrupt will be generated; if the CCxDE bit is preset, a DMA request will be generated.
  • Page 159 CH32L103 Reference Manual https://wch-ic.com 14.3.6 PWM Output Mode The PWM output mode is one of basic functions of timer. The most common method of PWM output mode is to use the reload value to determine the PWM frequency, and to use the capture comparison register to determine the duty cycle.

  • Page 160: Single Pulse Mode

    CH32L103 Reference Manual https://wch-ic.com be generated by CSS (Clock Security System). After the system reset, the break function will be disabled by default (MOE bit is low). Setting the BKE bit can enable the break function. The polarity of the input break signal can be set by setting BKP. The BKE and BKP signals can be written at the same time.
  • Page 161 CH32L103 Reference Manual https://wch-ic.com outputted by the encoder will increase the core counter by adding one or subtracting one. The steps to use the encoder are: set the SMS field to 001b (counting only on TI2 edge), 010b (counting only on TI1 edge) or 011b (counting on both TI1 and TI2 edges), and connect the encoder to compare/capture channel 1, 2 input terminals, set a value for the reload value register and this value can be set to be greater.
  • Page 162 CH32L103 Reference Manual https://wch-ic.com Figure 14-6 Control circuit in reset mode Counter clock =ck_cnt=ck_psc Counter 30 31 32 33 34 35 36 00 01 02 03 00 01 02 03 register Slave mode: Gated mode The level of the input signal enables the counter. In the following example, the counter counts up only when TI1 is low: 1) Configure channel 1 to detect a low level on TI1.
  • Page 163 CH32L103 Reference Manual https://wch-ic.com require any filter, so keep IC2F = 0000). There is no need to configure the capture divider as it is not used for trigger operation. the CC2S bit selects only the input capture source by setting CC2S=01 (in R16_TIMx_CCMR1). Write CC2P=1 and CC2NP='0' to the R16_TIMx_CCER register to verify polarity (detect low level only) 2) Write SMS=110 to R16_TIMx_SMCFGR register to configure the timer to trigger mode;...
  • Page 164 CH32L103 Reference Manual https://wch-ic.com Figure 14-9 Control circuit in external clock mode 2 + trigger mode CEN/CNT_EN Counter clock =CK_CNT=CK_PSC Counter register 14.3.12 Timer Synchronization Mode The TIMx timers are connected together from within to synchronize or cascade the timers. When a timer is configured in master mode, the counter of another timer configured in slave mode can be reset, started, stopped or clocked.
  • Page 165 CH32L103 Reference Manual https://wch-ic.com In this example Timer 2 is enabled by comparing the output of Timer 1 with 1. Timer 2 counts according to the divided internal clock only when OC1REF of Timer 1 is high. The clock frequency of both counters is based on CK_INT by prescaler performing a 3-way frequency (fCK_CNT=fCK_INT/3).
  • Page 166 CH32L103 Reference Manual https://wch-ic.com 10) Stop Timer 1 by writing "0" to the CEN bit (R16_TIM1_CTLR1 register). Figure 14-12 Gating Timer 2 using Timer 1's enable signal CK_INT TIMER1-CEN=CNT_EN TIMER1-CNT_INIT TIMER1-CNT TIMER2-CNT TIMER2-CNT_INIT TIMER2 WRITE TIMER2-TIF WRITE TIF=0 Using one timer to start another timer This example uses the update event of Timer 1 to enable Timer 2.
  • Page 167 CH32L103 Reference Manual https://wch-ic.com Figure 14-13 Triggering Timer 2 using Timer 1 update event CK_INT TIMER1 -UEV TIMER1 -CNT TIMER2 -CNT TIMER2 - CEN=CNT_EN TIMER2 -TIF WRITE TIF=0 As shown in the example above, the user can initialize both counters before starting to count. Figure 14-14 shows the counting behaviour with the same configuration as Figure 14-13, except in trigger mode (SMS=110 in the R16_TIM2_SMCFGR register) rather than gated mode.
  • Page 168 CH32L103 Reference Manual https://wch-ic.com 6) Timer 1 is started by writing "1" to the CEN bit (R16_TIM1_CTLR1 register). Synchronized start of 2 timers using an external trigger In this example, Timer 1 is enabled when there is a rising edge on the TI1 input of Timer 1, and Timer 2 is enabled at the same time as Timer 1.

  • Page 169: Register Description

    CH32L103 Reference Manual https://wch-ic.com 14.3.13 Debug Mode When the system enters debug mode, the timer continues to run or stops according to the settings of the DBG module. 14.4 Register Description Table 14-3 TIM1-related registers list Name Access address Description...
  • Page 170 CH32L103 Reference Manual https://wch-ic.com 0: The capture value is the value of the actual counter 1: The CHxCVR value is 0xFFFF when a counter overflow is generated before capture. Reserved Reserved TIM1 Brake input source selection: 0: Brake comes from IO or OPA;...
  • Page 171 CH32L103 Reference Manual https://wch-ic.com mode is not allowed. Counter direction: 0: The counting mode of the counter is increment. 1: The counting mode of the counter is subtractive. Note: This bit is not valid when the counter is configured in central alignment mode or encoder mode.
  • Page 172 CH32L103 Reference Manual https://wch-ic.com 14.4.2 Control Register 2 (TIM1_CTLR2) Offset address: 0x04 Reserved OIS4 OIS3N OIS3 OIS2N OIS2 OIS1N OIS1 TI1S MMS[2:0] CCDS CCUS Reserved CCPC Name Access Description Reset value Reserved Reserved Output idle state 4. 1: When MOE=0, if OC4N is implemented, OC1=1 after deadband;...
  • Page 173 CH32L103 Reference Manual https://wch-ic.com a trigger input, there is a delay on TRGO unless master/slave mode is selected (see the description of the MSM bit in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO).
  • Page 174 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value ETR trigger polarity selection, this bit selects whether to input ETR directly or to input the inverse of ETR. 1: Invert ETR, low or falling edge active; 0: ETR, active high or rising edge.
  • Page 175 CH32L103 Reference Manual https://wch-ic.com allow perfect synchronization between the current timer (via TRGO) and its slave timer. This is useful when the synchronization of several timers to a single external event is required. 0: Does not function. Trigger selection field, these 3 bits select the trigger input source used to synchronize the counter.
  • Page 176 CH32L103 Reference Manual https://wch-ic.com 14.4.4 DMA/Interrupt Enable Register (TIM1_DMAINTENR) Offset address: 0x0C Reserve COMD CC4D CC3D CC2D CC1D COMI CC4I CC3I CC2I CC1I Name Access Description Reset value Reserved Reserved Trigger the DMA request enable bit. 1: Allow DMA requests to be triggered.
  • Page 177 CH32L103 Reference Manual https://wch-ic.com Trigger the interrupt enable bit. 1: Enable triggering of interrupts. 0: Trigger interrupt is disabled. COM interrupt allow bit. COMIE 1: Allow COM interrupts. 0: COM interrupt is disabled. Compare capture channel 4 interrupt enable bit.
  • Page 178 CH32L103 Reference Manual https://wch-ic.com valid, by hardware for this position bit, can be cleared by software. 1: A set valid level is detected on the brake pin input. 0: No braking event is generated. Trigger interrupt flag bit, when a trigger event occurs by hardware to this location bit, by software to clear.
  • Page 179 CH32L103 Reference Manual https://wch-ic.com If URS = 0, UDIS = 0, when the UG bit is set, or when the counter core counter is reinitialized by software. If URS = 0, UDIS = 0, when the counter CNT is reinitialized by a trigger event.
  • Page 180 CH32L103 Reference Manual https://wch-ic.com This bit is set by software and cleared by hardware. It is used to generate a compare capture event. 1: Generate a compare capture event on compare capture channel 1. If compare capture channel 1 is configured as output.
  • Page 181 CH32L103 Reference Manual https://wch-ic.com The 3 bits define the action of the output reference signal OC2REF, which determines the values of OC2, OC2N. OC2REF is active high, while the active levels of OC2 and OC2N depend on the CC2P, CC2NP bits.
  • Page 182 CH32L103 Reference Manual https://wch-ic.com register 2, compare capture register 2 can be written at any time, and the newly written value takes effect immediately. Note: Once the LOCK level is set to 3 and CC2S=00, this bit cannot be modified; PWM mode can be used...
  • Page 183 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value The input capture filter 2 configuration field, these bits set the sampling frequency of the TI1 input and the digital filter length. The digital filter consists of an event counter, which records N events and then generates a jump in the output.
  • Page 184 CH32L103 Reference Manual https://wch-ic.com Note: CC1S is writable only when the channel is off (CC1E is 0). [7:4] IC1F[3:0] RW Input capture filter 1 configuration field. Compare the capture channel 1 prescaler configuration [3:2] IC1PSC[1:0] field. [1:0] CC1S[1:0] RW Compare capture channel 1 input selection fields.
  • Page 185 CH32L103 Reference Manual https://wch-ic.com 14.4.9 Compare/Capture Enable Register (TIM1_CCER) Offset address: 0x20 15 14 Reserve CC3N CC3N CC2N CC2N CC1N CC1N Name Access Description Reset value [15:14] Reserved Reserved CC4P Compare the capture channel 4 output polarity setting bit. CC4E Compare capture channel 4 output enable bit.
  • Page 186 CH32L103 Reference Manual https://wch-ic.com The CC1 channel is configured to enter: This bit determines whether the value of the counter can be captured into the TIMx_CCR1 register. 1: Capture enable. 0: Capture is prohibited. 14.4.10 Counter of Advanced-control Timer (TIM1_CNT)
  • Page 187 CH32L103 Reference Manual https://wch-ic.com 14.4.14 Compare/Capture Register 1 (TIM1_CH1CVR) Offset address: 0x34 Reserved LEVEL1 CCR1[15：0] Name Access Description Reset value [31:17] Reserved Reserved The level indicator bit corresponding to the capture LEVEL1 value [15:0] CCR1[15:0] RW Compare/capture register channel 1.
  • Page 188 CH32L103 Reference Manual https://wch-ic.com 14.4.17 Compare/Capture Register 4 (TIM1_CH4CVR) Offset address: 0x40 Reserved LEVEL4 CCR4[15：0] Name Access Description Reset value [31:17] Reserved Reserved The level indicator bit corresponding to the capture LEVEL4 value [15:0] CCR1[15:0] RW Compare/capture register channel 4.
  • Page 189 CH32L103 Reference Manual https://wch-ic.com level, then set OCx, OCxN enable output signal=1. 0: When the timer is not operating, OC/OCN output is disabled. Note: When LOCK level 1 is set, this bit cannot be modified. 1: when the timer is not operating, once CCxE = 1 or CCxNE = 1, OC/OCN first outputs its idle level, then OCx, OCxN enable output signal = 1.
  • Page 190 CH32L103 Reference Manual https://wch-ic.com The length of the DMA continuous transmission, the [12:8] DBL[4:0] actual value of which is the value of this field + 1. [7:5] Reserved Reserved These bits define the offset of the DMA in continuous [4:0]...

  • Page 191: Chapter 15 General-Purpose Timer (Gptm)

    CH32L103 Reference Manual https://wch-ic.com Chapter 15 General-Purpose Timer (GPTM) The general timer module consists of two 16-bit automatic reassembling timers (TIM2, TIM3) and a 32-bit automatic reinstalling timer (TIM4), which are used to measure pulse width or generate pulses and PWM waves with specific frequencies.
  • Page 192 CH32L103 Reference Manual https://wch-ic.com 15.2 Principle and Structure Figure 15-1 Block diagram of the structure of the general-purpose timer Internal clock(CK_INT) CK_TIM from RCC TRGO To DAC Trigger controller Reset, Enable, Up, Count AutoReload Register Stop, clear or up CK_PSC...
  • Page 193 CH32L103 Reference Manual https://wch-ic.com 15.2.2 Difference between General-purpose Timer and Advanced-control Timer Compared with the advanced-control timer, the general-purpose timer is lack of the following functions: 1) The general-purpose timer lacks a repeated counting register that counts the count cycle of core counter.
  • Page 194 CH32L103 Reference Manual https://wch-ic.com 15.2.3.2 External Clock Source Mode 1 If SMS is set to 111b, the external clock source mode1 is enabled. When external clock source mode1 is enabled, TRGI is selected as the source of CK_PSC. It is worth noting that the user needs to configure TS to select the source of TRGI.
  • Page 195 CH32L103 Reference Manual https://wch-ic.com Figure 15-3 Structure block diagram of compare/capture channel TI1F_ED To the slave mode controller TI1F_Rising TI1FP1 TI1F Filter Edge TI1F_Falling downcounter detector Divider TI2FP1 /1,/2,/4,/8 ICF[3:0] CC1P/CC1NP TIMx_CHCTLR1 TIMx_CCER (from slave mode controller) TI2F_Rising (from channel 2)
  • Page 196 CH32L103 Reference Manual https://wch-ic.com 15.3 Function and Implementation The general-purpose timer complex functions are implemented by the operation of compare/capture channel, clock input circuit, counter and peripheral parts of the timer. The timer's clock input can come from multiple clock sources including the input of the compare/capture.
  • Page 197 CH32L103 Reference Manual https://wch-ic.com 2) Set the count value to be compared to the compare/capture register (R16_TIMx_CHxCVR); 3) If an interrupt needs to be generated, set the CCxIE bit; 4) Keep OCxPE as 0 and disable the preload register of the compare/capture register;...

  • Page 198: Encoder Mode

    CH32L103 Reference Manual https://wch-ic.com  Edge alignment When the edge alignment is used, the core counter counts up or down. In the scenario of PWM mode 1, when the value of the core counter is greater than that of the compare/capture register, OCxREF will rise to be high; when the value of the core counter is less than the compare/capture register (such as When the core counter increases to the value of R16_TIMx_ATRLR and returns to all 0s), OCxREF drops to low.

  • Page 199: Register Description

    CH32L103 Reference Manual https://wch-ic.com edges), and connect the encoder to compare/capture 1, 2 inputs, set a value for the reload value register and this value can be set to be greater. In the encoder mode, the internal compare/capture register of timer, prescaler, repeat count register and other registers all work normally.
  • Page 200 CH32L103 Reference Manual https://wch-ic.com R16_TIM2_CHCTLR2 0x4000001C TIM2 compare/capture control register 2 0x0000 R16_TIM2_CCER 0x40000020 TIM2 compare/capture enable register 0x0000 R16_TIM2_CNT 0x40000024 TIM2 counter 0x0000 R16_TIM2_PSC 0x40000028 TIM2 prescaler 0x0000 R16_TIM2_ATRLR 0x4000002C TIM2 auto-reload register 0xFFFF R32_TIM2_CH1CVR 0x40000034 TIM2 compare/capture register 1...
  • Page 201 CH32L103 Reference Manual https://wch-ic.com R16_TIM4_SWEVGR 0x40000814 TIM4 event generation register 0x0000 R16_TIM4_CHCTLR1 0x40000818 TIM4 compare/capture control register1 0x0000 R16_TIM4_CHCTLR2 0x4000081C TIM4 compare/capture control register2 0x0000 R16_TIM4_CCER 0x40000820 TIM4 compare/capture enable register 0x0000 R16_TIM4_CNT 0x40000824 TIM4 counter 0x00000000 R16_TIM4_PSC 0x40000828 TIM4 prescaler...
  • Page 202 CH32L103 Reference Manual https://wch-ic.com 00: Edge alignment mode. The counter counts up or down according to the direction bit (DIR). 01: Center alignment mode 1. The counter counts up and down alternately. The output comparison interrupt flag bit of the channel configured as an output (CCxS=00 in the CHCTLRx register) is only set when the counter counts down.
  • Page 203 CH32L103 Reference Manual https://wch-ic.com values. Updates are prohibited, and the software allows / disables the generation of UEV events through this bit. 1: UEV is prohibited. No update events are generated, and the registers (ATRLR, PSC, CHCTLRx) hold their values. If the UG bit is set or a hardware reset is issued from the mode controller, the counter and prescaler are reinitialized.
  • Page 204 CH32L103 Reference Manual https://wch-ic.com 001: Enable-the counter enables signal CNT_EN to be used as a trigger output (TRGO). Sometimes, it is necessary to start multiple timers at the same time or control to enable slave timers within a period of time.
  • Page 205 CH32L103 Reference Manual https://wch-ic.com trigger mode; however, TRGI cannot be connected to ETRF at this time (TS bit cannot be 111b). Note 2: When both external clock mode 1 and external clock mode 2 are enabled at the same time, the input of the external clock will be ETRF.
  • Page 206 CH32L103 Reference Manual https://wch-ic.com 100: Edge detector of TI1 (TI1F_ED); 101: Timer input 1 (TI1FP1) after filtering; 110: Timer input 2 (TI12FP2) after filtering; 111: External trigger input (ETRF); The values can be changed only when SMS is 0. Reserved Reserved Input mode selection.
  • Page 207 CH32L103 Reference Manual https://wch-ic.com DMA request enable of compare/capture3. CC3DE 1: DMA request of compare/capture3 enabled; 0: DMA request of compare/capture3 disabled. DMA request enable of compare/capture2. CC2DE 1: DMA request of compare/capture2 enabled; 0: DMA request of compare/capture2 disabled.
  • Page 208 CH32L103 Reference Manual https://wch-ic.com Compare/capture1 recapture flag is only used when the compare/capture is configured in the input capture mode. This flag bit is set by the hardware, write 0 by software to clear the bit. CC1OF 1: When the value of the counter is captured into the capture comparison register, the status of CC1IF has been set;...
  • Page 209 CH32L103 Reference Manual https://wch-ic.com counter core is reinitialized by software; For URS=0, UDIS=0, when the counter CNT is reinitialized by a trigger event. 15.4.6 Event Generation Register (TIMx_SWEVGR) (x=2/3/4) Offset address: 0x14 Reserved TG Reserved CC4G CC3G CC2G CC1G UG...
  • Page 210 CH32L103 Reference Manual https://wch-ic.com will be cleared; in the down-counting mode, the core counter will take the value of the reload value register. 15.4.7 Compare/Capture Control Register 1 (TIMx_CHCTLR1) (x=2/3/4) Offset address: 0x18 The channel can be used for input (capture mode) or output (compare mode), and the direction of the channel is defined by the corresponding CCxS bit.
  • Page 211 CH32L103 Reference Manual https://wch-ic.com downward counting, once the core counter is greater than the value of the compare capture register, channel 2 is invalid level (OC2REF=0), otherwise it is valid level (OC2REF=1). 111: PWM mode 2: In up count, once the core counter...
  • Page 212 CH32L103 Reference Manual https://wch-ic.com compare/capture 2 is 5 clock cycles. OC2FE only works when the channel is configured in PWM1 or PWM2 mode. Compare/capture 2 input selection. 00: The compare/capture 2 is configured as output; 01: Compare/capture 2 is configured as input, and IC2 is mapped on TI2;...
  • Page 213 CH32L103 Reference Manual https://wch-ic.com Compare/capture 2 prescaler configuration. These 2 bits define the prescaler factor of compare/capture 2. Once CC1E=0, the prescaler will be reset. 00: Prescaler OFF, each edge detected on the capture [11:10] IC2PSC[1:0] input port triggers a capture;...
  • Page 214 CH32L103 Reference Manual https://wch-ic.com [9:8] CC4S[1:0] RW Compare/capture 4 input selection OC3CE RW Compare/capture 3 clear enable [6:4] OC3M[2:0] RW Compare/capture 3 mode setting OC3PE RW Compare/capture 3 preload enable OC3FE RW Compare/capture 3 fast enable [1:0] CC3S[1:0] RW Compare/capture 3 input selection...
  • Page 215 CH32L103 Reference Manual https://wch-ic.com [15:0] CNT[15:0] RW Real-time value of timer counter. 15.4.11 Counter of General-purpose Timer (TIMx_CNT) (x=4) Offset address: 0x24 CNT[31:16] CNT[15:0] Name Access Description Reset value [31:0] CNT[31:0] RW Real-time value of timer counter. 15.4.12 Prescaler (TIMx_PSC) (x=2/3/4)
  • Page 216 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value The value of ATRLR[31:0] is loaded into the counter. 0xFFFFFFF [31:0] ARR[31:0] Please refer to Section 15.2.4 for ATRLR acting and update time. When ATRLR is empty, the counter stops. 15.4.15 Compare/Capture Register 1 (TIMx_CH1CVR) (x=2/3)
  • Page 217 CH32L103 Reference Manual https://wch-ic.com value [15:0] CCR2[15:0] RW Compare/capture register channel 2. 15.4.18 Compare/Capture Register2 (TIMx_CH2CVR) (x=4) Offset address: 0x38 CCR2[31：16] CCR2[15：0] Name Access Description Reset value [31:0] CCR2[31:0] RW Compare/capture register channel 2. 15.4.19 Compare/Capture Register3 (TIMx_CH3CVR) (x=2/3) Offset address: 0x3C...
  • Page 218 CH32L103 Reference Manual https://wch-ic.com Reserved LEVEL4 CCR4[15：0] Name Access Description Reset value [31:17] Reserved Reserved The level indicator bit corresponding to the capture LEVEL4 value [15:0] CCR4[15:0] RW Compare/capture register channel 4. 15.4.22 Compare/Capture Register4 (TIMx_CH4CVR) (x=4) Offset address: 0x40...
  • Page 219 CH32L103 Reference Manual https://wch-ic.com DMAB[15:0] Name Access Description Reset value [31:0] DMAB[31:0] RW DMA address in continuous mode. V1.9...

  • Page 220: Chapter 16 Low-Power Timer (Lptim)

    CH32L103 Reference Manual https://wch-ic.com Chapter 16 Low-power Timer (LPTIM) LPTIM is a 16-bit uplink count timer. LPTIM has a variety of optional clock sources that allow LPTIM to operate in all power modes except standby mode. LPTIM can also run without an internal clock source, so LPTIM can be used as a "pulse counter".

  • Page 221: Lptim Trigger Mapping

    CH32L103 Reference Manual https://wch-ic.com 16.2 Function Description 16.2.1 LPTIM Structure Figure 16-1 Block diagram of LPTIM LPTIM PB_ITF Kemel Up/dowm Input2 Glitch Encoder (LPTIM filter _CH2) Input1 Glitch (LPTIM filter _CH2) Up to 8 ext trigget Glitch trigget filter 16-bit ARR...
  • Page 222 CH32L103 Reference Manual https://wch-ic.com When using the internal clock source count, the internal clock source can select the four PB1, LSI, LSE, HIS clock sources through the CLKMX_SEL bit of the LPTIM_CFGR register. In addition, the LPTIM can be timed using an external clock signal injected on the external input LPTIM_CH1 (PB5/PB12).

  • Page 223: Trigger Multiplexer

    CH32L103 Reference Manual https://wch-ic.com Figure 16-2 Timing block diagram of interference filter CLKMUX Input Filter out 2 consecutive 2 consecutive Filtered samples samples Note: when the internal clock signal is not used, the digital filter must be disabled by zeroing the CKFLT and TRGFLT bits, and using an external analog filter to avoid interference caused by the external input of the LPTIM.

  • Page 224: Operating Mode

    CH32L103 Reference Manual https://wch-ic.com Table 16-5 Trigger source TRIGSEL[1:0] Trigger source LPTIM_ETR(PB6/PB14) RTC_ALARM TAMPER (PC13) Invalid 16.3.5 Operating Mode LPTIM has 2 modes of operation: Continuous mode: the timer runs freely, starting from the trigger event and not stopping until the timer is disabled.

  • Page 225: Timeout Function

    CH32L103 Reference Manual https://wch-ic.com Figure 16-4 LPTIM output waveform for single count mode configuration with one setup mode activated Compare Discarded trigger External trigger event In continuous mode, to enable continuous counting, the CNTSTRT bit must be set, and if an external trigger is selected, external trigger events that arrive after setting CNTSTRT will start the counter for continuous counting.

  • Page 226: Waveform Generation

    CH32L103 Reference Manual https://wch-ic.com 16.3.7 Waveform Generation Two 16-bit registers LPTIM_ARR and LPTIM_CMP are used to generate several different waveforms on the LPTIM output. The timer can generate the following waveforms: (1) PWM mode: once the counter value in LPTIM_CNT exceeds the comparison value in LPTIM_CMP, the LPTIM output is set.

  • Page 227: Register Update

    CH32L103 Reference Manual https://wch-ic.com Figure 16-6 Waveform generation Compare Pol = 0 One shot Set shot One shot Pol = 1 Set shot 16.3.8 Register Update The LPTIM_ARR register and the LPTIM_CMP register are updated immediately after the PB bus write operation, or if the timer has been started, at the end of the current cycle.
  • Page 228 CH32L103 Reference Manual https://wch-ic.com CKSEL and count bits control which source will be used to update the counter. If the LPTIM is configured to count external events on the LPTIM_CH1, the count can be updated after the rising, falling, or double edges based on the values written to the CKPOL [1:0] bit.
  • Page 229 CH32L103 Reference Manual https://wch-ic.com are obtained, in which LPTIM_CH1 and LPTIM_CH2 do not switch at the same time. Table 16-7 Configuration of edge sensitivity combination scheme The level of the opposite LPTIM_CH1 LPTIM_CH2 signal (The input for Active edge LPTIM_CH1...

  • Page 230: Register Description

    CH32L103 Reference Manual https://wch-ic.com is equal to that of the automatic reload register LPTIM_ARR External trigger event An interrupt flag is generated when an externally triggered event is detected Automatic overload register An interrupt flag is generated when the write operation to the LPTIM_ARR write complete register is completed.
  • Page 231 CH32L103 Reference Manual https://wch-ic.com 1: Counting direction from top to bottom. 0: Invalid. In encoder mode, this bit is set by hardware to notify the application of a change in counter direction from top to bottom, which can be cleared by writing 1 to the LPTIM_ICR [6] bit.
  • Page 232 CH32L103 Reference Manual https://wch-ic.com LPTIM_CNT register. 1: Match successfully. 0: Invalid. This bit is set by the hardware to inform the application that the value of the LPTIM_CNT register reaches the value of the LPTIM_CMR register, which can be cleared by writing 1 to the LPTIM_ICR [0] bit.
  • Page 233 CH32L103 Reference Manual https://wch-ic.com 16.5.3 Interrupt Enable Register (LPTIM_IER) Offset address: 0x08 31 30 29 28 27 26 25 24 23 Reserved 14 13 12 11 10 9 Reserved DOWNIE UPIE ARROKIE CMPOKIE EXTTRIGIE ARRMIE CMPMIE Name Access Description Reset value...
  • Page 234 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [31:28] Reserved Reserved Force PWM output FORCE_PWM 0: Invalid. 1: Force PWM output high level LPTIM counter internal clock source selection 00: TIM_CLK (from PB1_CLK) [26:25] CLKMX_SEL 01: HSI_CLK 10: LSE_CLK...
  • Page 235 CH32L103 Reference Manual https://wch-ic.com 01: Rising edge trigger. 10: Falling edge trigger. 11: Double edge trigger. [16:15] Reserved Reserved Trigger source selection 00: LPTIM_ETR (PB6/PB14) [14:13] TRIGSEL 01: RTC_ALARM 10: TAMPER (PC13) 11: Invalid. Reserved Reserved Clock prescaler, configured with prescaler...
  • Page 236 CH32L103 Reference Manual https://wch-ic.com at least 2 clock cycles before they are considered valid. 10: External clock signal level changes must be stable for at least 4 clock cycles before they are considered valid. 11: External clock signal level changes must be stable for at least 8 clock cycles before they are considered valid.
  • Page 237 CH32L103 Reference Manual https://wch-ic.com be effective. Start in continuous mode. This bit is set by the software and cleared by the hardware. In the case of software startup (TRIGEN==00), set this bit to start the LPTIM in continuous mode, and if the software...
  • Page 238 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value The count register reloaded count value. When counting up, if the count value is equal to the reloaded count value, [15:0] the counter starts counting from 0; when counting down, if the counter value equals 0, the count starts from the reloaded count value.

  • Page 239: Chapter 17 Universal Synchronous Asynchronous Receiver

    CH32L103 Reference Manual https://wch-ic.com Chapter 17 Universal Synchronous Asynchronous Receiver Transmitter (USART) The module contains 4 universal synchronous asynchronous transceivers (USART1/2/3/4). 17.1 Main Features  Full-duplex or half-duplex synchronous or asynchronous communication  NRZ data format  Fractional baud rate generator, highest 6Mbps ...

  • Page 240: Baud Rate Generator

    CH32L103 Reference Manual https://wch-ic.com 17.2 Overview Figure 17-1 USART block diagram When TE (transmission enable bit) is set, the data in the transmitter shift register will be outputted on the TX pin, and the clock will be outputted on the CK pin. During transmission, the lowest significant bit is the first to be shifted out.

  • Page 241: Synchronous Mode

    CH32L103 Reference Manual https://wch-ic.com is used for the USART1 module, and PCLK1 shall be used for the rest. The value of USARTDIV is determined according to the 2 domains: DIV_M and DIV_F in USART_BRR. The specific calculation formula is: USARTDIV = DIV_M+(DIV_F/16) It should be noted that the baud rate generated by the baud rate generator may not always generate just the baud rate required by the user, which may be biased.
  • Page 242 CH32L103 Reference Manual https://wch-ic.com Figure 17-2 Example of USART clock timing (M=0) Figure 17-3 Data sample hold time CK (capture strobe on CK rising edge in this example) Data on RX valid DATA bit (from slave) SETUP HOLD 1/16 bit time...

  • Page 243: Smart Card

    CH32L103 Reference Manual https://wch-ic.com mode. This requires users to avoid it by software. 17.6 Smart Card The smartcard mode supports ISO7816-3 protocol to access the smart card controller. To enable smartcard mode, set the SCEN bit in the control register 3 (R16_USARTx_CTLR3), but it is needed to disable LIN mode, half-duplex mode and infrared mode at the same time, i.e., to ensure that the LINEN, HDSEL...

  • Page 244: Register Description

    CH32L103 Reference Manual https://wch-ic.com represents low level. However, in the SIR transmit logic, ‘0’ represents high level and ‘1’ represents low level. 17.8 DMA The USART module supports DMA, and can use DMA to implement fast continuous reception and transmission.
  • Page 245 CH32L103 Reference Manual https://wch-ic.com Table 17-3 USART2-related registers Name Access address Description Reset value R32_USART2_STATR 0x40004400 UASRT2 status register 0x000000C0 R32_USART2_DATAR 0x40004404 UASRT2 data register 0x000000XX R32_USART2_BRR 0x40004408 UASRT2 baud rate register 0x00000000 R32_USART2_CTLR1 0x4000440C UASRT2 control register1 0x00000000 R32_USART2_CTLR2...
  • Page 246 CH32L103 Reference Manual https://wch-ic.com the nCTS output state changes, the bit will be set high by the hardware. Zero is cleared by the software. If the CTSIE bit has been set, an interrupt occurs. 1: There is a change in the nCTS state line.
  • Page 247 CH32L103 Reference Manual https://wch-ic.com Overrun error flag. When the receiving shift register has data that needs to be transferred to the data register, but this bit will be set when there is still data that has not been read in the receiving field of the data register.
  • Page 248 CH32L103 Reference Manual https://wch-ic.com Reserved Reserved DR[8:0] Name Access Description Reset value [31:9] Reserved Reserved Data register. This register is actually composed of 2 registers: receive data register (RDR) and transmit [8:0] DR[8:0] data register (TDR). The start of the read and write operations of DR is to read the receive data register (RDR) and write to the transmit data register (TDR).
  • Page 249 CH32L103 Reference Manual https://wch-ic.com 0: 8 data bits. Wake-up. This bit decides the method to wake up USART: WAKE 1: Address flag; 0: Idle line. Parity control enable. For the receiver, the parity of the data is performed; for the transmitter, the check bit is inserted.
  • Page 250 CH32L103 Reference Manual https://wch-ic.com the bit is set by hardware. 1: Break character transmitted; 0: No break character transmitted. 17.10.5 USART Control Register 2 (USARTx_CTLR2) (x=1/2/3/4) Offset address: 0x10 19 18 17 Reserved Reserved LINEN STOP CLKEN CPOL CPHA LBCL Reserved LBDIE LBDL Reserved...
  • Page 251 CH32L103 Reference Manual https://wch-ic.com transmission. Last bit clock pulse control. In synchronous mode, it is used to control whether to output the clock pulse corresponding to the last data byte sent on the CK pin; LBCL 1: The clock pulse of the last bit of data is not output from 0: The clock pulse of the last bit of data is output from CK.
  • Page 252 CH32L103 Reference Manual https://wch-ic.com Smart card mode enable. When this bit is set, smartcard SCEN mode is enabled. Smart card NACK enable. When this bit is set, NACK NACK is transmitted when the check error occurs. Half-duplex mode selection. When this bit is set, half- HDSEL duplex mode is selected.

  • Page 253: Chapter 18 Inter-Integrated Circuit (I2C) Interface

    CH32L103 Reference Manual https://wch-ic.com Chapter 18 Inter-integrated Circuit (I2C) Interface The internal integrated circuit bus (I2C) is widely used in the communication between microcontrollers, sensors and other off-chip modules. It supports multi-master and multi-slave mode, and can communicate at both 100KHz (standard) and 400KHz (fast) speeds using only two wires (SDA and SCL).

  • Page 254: Master Mode

    CH32L103 Reference Manual https://wch-ic.com For normal use, the correct clock must be input to I2C. In the standard mode, the minimum input clock is 2MHz, while the minimum input clock is 4MHz in the fast mode. Figure 18-2 shows the block diagram of I2C.
  • Page 255 CH32L103 Reference Manual https://wch-ic.com If the 10-bit address mode is enabled, then write the data register to send the header sequence (the header sequence is 11110xx0b, of which the xx bits are the highest 2 bits of the 10-bit address).

  • Page 256: Slave Mode

    CH32L103 Reference Manual https://wch-ic.com When the master device ends sending data, it will actively send an end event, that is, setting the STOP bit. In the receive mode, the master device needs to NAK at the answer location of the last data bit. Note that after the NAK is generated, the I2C module will switch to slave mode.
  • Page 257 CH32L103 Reference Manual https://wch-ic.com signal and start waiting for the address or stop signal; if it is a stop signal, it will operate according to the normal stop condition in advance. In main mode, the hardware does not release the bus and does not affect the current transmission, and it is up to the user code to decide whether to abort the transmission.
  • Page 258 CH32L103 Reference Manual https://wch-ic.com Similarities between SMBus and I2C: 1) Master-slave communication mode; the host provides the clock and supports multiple masters and multiple slaves; 2) 2-wire communication structure, of which a warning line can be selected for SMBus; 3) Support 7-bit address format.

  • Page 259: Packet Error Checking

    CH32L103 Reference Manual https://wch-ic.com The DMA mode can be activated by setting the DMAEN bit in the CTLR2 register. As long as the TxE bit is set, the data can be loaded into the I2C data register from the set memory by DMA. The following settings are required to allocate channels for I2C.

  • Page 260: Register Description

    CH32L103 Reference Manual https://wch-ic.com 18.11 Debug Mode After the system enters the debug mode, the DBG_I2Cx_SMBUS_TIMEOUT bit in the DEBUG module can be used to determine whether to continue operating or stop the time-out control of I2CSMBus. 18.12 Register Description...
  • Page 261 CH32L103 Reference Manual https://wch-ic.com pins of the I2C bus are released and the bus is idle. Note: This bit can reset the I2C module when no stop condition is detected on the bus but the busy bit is 1. Reserved Reserved.
  • Page 262 CH32L103 Reference Manual https://wch-ic.com code, or cleared by hardware when a stop event is detected, or set by hardware when a timeout error is detected. In master mode: 1: A stop event is generated after the current byte transfer or the current start condition is issued;...
  • Page 263 CH32L103 Reference Manual https://wch-ic.com Offset address: 0x04 ITBU ITEV ITER Reserved LAST Reserved FREQ[5:0] Name Access Description Reset value [15:13] Reserved Reserved Last transfer setting of DMA. 1: Next DMA EOT is the last transfer; 0: Next DMA EOT is not the last transfer.
  • Page 264 CH32L103 Reference Manual https://wch-ic.com Offset address: 0x08 Reserved ADD[9:8] ADD[7:1] Name Access Description Reset value Addressing mode. 10-bit slave address (7-bit address ADDMODE acknowledged); 7-bit slave address (10-bit address acknowledged). [14:10] Reserved Reserved. Interface address, which is 9-8 bits when using 10-bit...
  • Page 265 CH32L103 Reference Manual https://wch-ic.com 18.12.6 I2C Status Register 1 (I2Cx_STAR1) (x=1/2) Offset address: 0x14 SMBA TIME Reser PECE Reser STOP TxE RxNE LERT Name Access Description Reset value SMBus alert. It can be reset by user writing 0, or reset by hardware when PE becomes low.
  • Page 266 CH32L103 Reference Manual https://wch-ic.com 0: No overrun and underrun event. Acknowledge failure flag. This bit can be reset by user writing 0, or reset by hardware when PE becomes low. 1: Acknowledge error; 0: Normal acknowledge. Arbitration lost flag. It can be reset by user writing 0, or reset by hardware when PE becomes low.
  • Page 267 CH32L103 Reference Manual https://wch-ic.com the status register1, reading and writing to the data register will clear this bit. During transmission, after a start or stop event is initiated, or when PE is 0, this bit will be cleared by hardware.
  • Page 268 CH32L103 Reference Manual https://wch-ic.com this bit. 1: The received address matched with OAR2; 0: The received address matched with OAR1. SMBus host header flag. When the stop bit or start bit is generated, or when PE=0, the hardware will clear this bit.
  • Page 269 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value Master mode selection. 1: Fast mode; 0: Standard mode. Duty cycle in the fast mode: DUTY 1: T =16/9; Low level High level 0: T Low level High level [13:12] Reserved Reserved.

  • Page 270: Chapter 19 Serial Peripheral Interface (Spi)

    CH32L103 Reference Manual https://wch-ic.com Chapter 19 Serial Peripheral Interface (SPI) SPI supports data exchange in three-wire synchronous serial mode, plus chip line selection supports hardware switching between master and slave modes, and supports communication with a single data line. 19.1 Main Features 19.1.1 SPI Features...
  • Page 271 CH32L103 Reference Manual https://wch-ic.com As can be seen from Figure 19-1, the 4 pins related to SPI are MISO, M0SI, SCK and NSS. The MISO pin is the data input pin when the SPI module works in the master mode; it is the data output pin when it works in the slave mode.
  • Page 272 CH32L103 Reference Manual https://wch-ic.com set, it will also generate interrupt. At this time, the data register should be read as soon as possible to remove the data. Figure 19-2 SPI master mode read/write mode 0 MODE 0 CPHA=0 CPOL=0 MOSI...
  • Page 273 CH32L103 Reference Manual https://wch-ic.com Figure 19-4 SPI master mode read/write mode 2 MODE 2 CPHA=1 CPOL=0 CPOL=0 LSBit MOSI MSBit MISO MSBit LSBit (to slave) Capture strobe Figure 19-5 SPI master mode read/write mode 3 MODE 3 CPHA=1 CPOL=1 LSBit...
  • Page 274 CH32L103 Reference Manual https://wch-ic.com Configure LSBFIRST to match the host data frame format; In hardware management mode, the NSS pin needs to be kept at a low level. If NSS is set to software management (SSM is set), then please keep SSI not set;...
  • Page 275 CH32L103 Reference Manual https://wch-ic.com Figure 19-8 SPI slave mode read/write mode 2 MODE 2 CPHA=1 CPOL=0 CPOL=0 LSBit MOSI MSBit MISO MSBit LSBit (to slave) Capture strobe Figure 19-9 SPI slave mode read/write mode 3 MODE 3 CPHA=1 CPOL=1 LSBit...

  • Page 276: Register Description

    CH32L103 Reference Manual https://wch-ic.com 19.2.5 CRC The SPI module uses CRC to ensure the reliability of full-duplex communication, and separate CRC calculators are used for data transmission and reception. The polynomial of the CRC calculation is determined by the polynomial register.
  • Page 277 CH32L103 Reference Manual https://wch-ic.com R16_SPI1_CTLR1 0x40013000 SPI1 control register 1 0x0000 R16_SPI1_CTLR2 0x40013004 SPI1 control register 2 0x0000 R16_SPI1_STATR 0x40013008 SPI1 status register 0x0002 R16_SPI1_DATAR 0x4001300C SPI1 data register 0x0000 R16_SPI1_CRCR 0x40013010 SPI1 polynomial register 0x0007 R16_SPI1_RCRCR 0x40013014 SPI1 receive CRC register...
  • Page 278 CH32L103 Reference Manual https://wch-ic.com 1: Transmit the CRC result; 0: Continue to transmit the data of the data register. Data frame length, this bit can only be written when SPE is 0. 1: Use 16-bit data length to transmit and receive;...
  • Page 279 CH32L103 Reference Manual https://wch-ic.com 1: In idle state, SCK remains high; 0: In idle state, SCK remains low. Clock phase setting. It cannot be modified during communication. CPHA 1: Data sampling starts from the second clock edge; 0: Data sampling starts from the first clock edge.
  • Page 280 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [15:8] Reserved Reserved Busy flag. Set and reset by hardware. 1: SPI is communicating, or the transmit buffer is not empty; 0: SPI is not communicating. Overflow flag. Set by hardware, and reset by software.
  • Page 281 CH32L103 Reference Manual https://wch-ic.com for data transmission, only the lower 8 bits of the data register are used, and the high 8 bits are forced to 0 when received. The use of 16-bit data structures causes all 16-bit data registers to be used.
  • Page 282 CH32L103 Reference Manual https://wch-ic.com register when BSY is 0. 19.3.8 SPI High-speed Control Register (SPIx_HSCR) (x=1/2) Offset address: 0x24 Reserved Name Access Description Reset value [15:1] Reserved Reserved Read enable in SPI high-speed mode. HSRXEN 1: High-speed read mode enabled;...

  • Page 283: Chapter 20 Usb Full-Speed Host/Device Controller (Usbfs)

    CH32L103 Reference Manual https://wch-ic.com Chapter 20 USB Full-speed Host/Device Controller (USBFS) 20.1 USB Controller Introduction Embedded USB2.0 controller and USB-PHY, with dual roles of host controller and USB device controller. When used as a host controller, it supports low-speed, full-speed and high-speed USB devices / HUB. When used as a device controller, it can be flexibly set to low-speed, full-speed or high-speed mode to adapt to a variety of applications.
  • Page 284 CH32L103 Reference Manual https://wch-ic.com value of 1 enables USB device transfer and enables the internal pull-up resistor. MASK_UC_SYS_CTR [5:4] See the table below to configure USB system. The USB transmission completion interrupt flag automatically pauses the enable bit before zero is cleared:...
  • Page 285 CH32L103 Reference Manual https://wch-ic.com 20.2.1.2 USB Interrupt Enable Register (R8_USB_INT_EN) Name Access Description Reset value Reserved Reserved USB device mode, receive NAK interrupt: RB_UIE_DEV_NAK 1: Enable interrupt; 0: Disable interrupt. USB 1-wire mode enable RB_UID_1_WIRE 1: Enable 0: Disable FIFO overflow interrupt: RB_UIE_FIFO_OV 1: Enable interrupt;...
  • Page 286 CH32L103 Reference Manual https://wch-ic.com USB protocol handler free: RB_UMS_SIE_FREE 1: The protocol device is free; 0: Busy, USB transfer in progress. USB receive FIFO data ready: RB_UMS_R_FIFO_RD 1: The receive FIFO is not empty; 0: The receive FIFO is empty.
  • Page 287 CH32L103 Reference Manual https://wch-ic.com flag, write 1 to clear: 1: Triggered by USB suspend event or wake- up event; 0: No event. USB bus suspend or wake-up event interrupt flag, write 1 to clear: RB_UIF_SUSPEND 1: Triggered by USB suspend event or wake- up event;...
  • Page 288 CH32L103 Reference Manual https://wch-ic.com MASK_UIS_TOKEN is used to identify the token PID of the current USB transfer transaction in the USB device mode: 00 means OUT packet; 01 reserved; 10 means IN packet; 11 means SETUP packet. MASK_UIS_H_RES is only valid in host mode. In the host mode, if the host sends the OUT/SETUP token packet, the PID is the handshake packet ACK/NAK/STALL, or the device has no response/timeout.
  • Page 289 CH32L103 Reference Manual https://wch-ic.com interrupt of USB transmission or reception, the synchronization trigger bit of the corresponding endpoint should be modified correctly to detect whether the data packet sent or received next time is synchronized; in addition, setting RB_UEP_T_AUTO_TOG or RB_UEP_R_AUTO_TOG can automatically modify the corresponding synchronization trigger bit (flip or self-subtraction) after successful transmission or reception.
  • Page 290 CH32L103 Reference Manual https://wch-ic.com R32_USB_EP6_CTRL 0x50000048 Endpoint 6 transmit length and control register 0x000000XX R16_UEP6_T_LEN 0x50000048 Endpoint 6 transmit length register 0x00XX R16_UEP6_CTRL 0x5000004A Endpoint 6 control register 0x0000 R32_USB_EP7_CTRL 0x5000004C Endpoint 7 transmit length and control register 0x000000XX R16_UEP7_T_LEN...
  • Page 291 CH32L103 Reference Manual https://wch-ic.com RB_UEP1_BUF_MOD Endpoint 1 data buffer mode control bit. 1: Enable endpoint 4 to receive (OUT). RB_UEP4_RX_EN 0: Disable endpoint 4 to receive. 1: Enable endpoint 4 to transmit (IN). RB_UEP4_TX_EN 0: Disable endpoint 4 to transmit.
  • Page 292 CH32L103 Reference Manual https://wch-ic.com 1: Enable endpoint 7 to transmit (IN). RB_UEP7_TX_EN 0: Disable endpoint 7 to transmit. Reserved Reserved RB_UEP7_BUF_MOD Endpoint 7 data buffer mode control bit. The data buffer modes of USB endpoints 1-15 are configured by the combination of RB_UEPn_RX_EN and RB_UEPn_TX_EN and RB_UEPn_BUF_MOD, respectively, with specific reference to Table 20-4.
  • Page 293 CH32L103 Reference Manual https://wch-ic.com Set the number of data bytes n=0, 1 that USB [6:0] R8_UEPn_T_LEN endpoint n is ready to send. 20.2.2.9 Endpoint n transmit length register (R16_UEPn_T_LEN) (n=2) Name Access Description Reset value [15:8] Reserved Reserved HOST_PID3 PID in host mode [3].
  • Page 294 CH32L103 Reference Manual https://wch-ic.com 10: Answer NAK or busy. 11: Answer STALL or error. [7:4] Reserved Reserved Synchronous trigger bit auto flip enable control bit: 1: Automatically flip the corresponding RB_UEP_T_AUTO_ synchronous trigger bit after the data is sent successfully.
  • Page 295 CH32L103 Reference Manual https://wch-ic.com successful transmission or reception. The USB host token setting register R8_UH_EP_PID is used to set the terminal number of the target device to be operated and the token PID packet identification of the USB transmission transaction. The data corresponding to the SETUP token and the OUT token are provided by the host sending endpoint, the data to be sent is in the R16_UH_TX_DMA buffer zone, and the length of the data to be sent is set in the R16_UH_TX_LEN;...
  • Page 296 CH32L103 Reference Manual https://wch-ic.com USB device is disconnected. 20.2.3.2 USB Host Endpoint Mode Control Register (R8_UH_EP_MOD) Name Access Description Reset value Reserved Reserved Host send endpoint transmit (SETUP/OUT) enable bit: RB_UH_EP_TX_EN 1: Enable endpoint to transmit. 0: Enable endpoint to transmit.
  • Page 297 CH32L103 Reference Manual https://wch-ic.com 20.2.3.3 USB Host Receive Buffer Start Address (R16_UH_RX_DMA) Name Access Description Reset value Host endpoint data receive buffer starting address. [15:0] R16_UH_RX_DMA XXXXh The lower 15 bits are valid and the address must be 4 bytes aligned.
  • Page 298 CH32L103 Reference Manual https://wch-ic.com Synchronous trigger bit auto flip enable control bit: 1: Automatically flip the corresponding RB_UH_R_AUTO_TO expected synchronous trigger (RB_UH_R_TOG) after successful data reception. 0: Do not flip automatically, you can switch manually. The synchronization trigger bits expected by...
  • Page 299 CH32L103 Reference Manual https://wch-ic.com 1: No response is expected for real-time / synchronous transmission non-zero endpoints. 0: Expect to reply ACK. V1.9...

  • Page 300: Chapter 21 Usb Pd Controller (Usbpd)

    CH32L103 Reference Manual https://wch-ic.com Chapter 21 USB PD Controller (USBPD) 21.1 USB PD Controller Introduction The chip has built-in USB Power Delivery controller and PD transceiver PHY, supports USB Type-C master-slave detection, automatic BMC codec and CRC, hardware edge control, supports USB PD2.0 and PD3.0 power transmission control, supports fast charging, supports UFP/DFP/DRD/DRP and PDUSB, and supports PD power receiving and PD power supply applications.
  • Page 301 CH32L103 Reference Manual https://wch-ic.com [31:16] R16_BMC_CLK_CNT [15:0] R16_CONFIG 21.2.2 PD Interrupt Enable Register (R16_CONFIG) Offset address: 0x00 IE_T IE_R IE_R PD_R PD_D PD_A IE_P CC_S Reser Reserved E_PO ST_E LL_C D_IO Name Access Description Reset value IE_TX_END End-of-transmit interrupt enable.
  • Page 302 CH32L103 Reference Manual https://wch-ic.com 21.2.3 BMC Sampling Clock Counter (R16_BMC_CLK_CNT) Offset address: 0x02 Reserved BMC_CLK_CNT Name Access Description Reset value [15:9] Reserved Reserved BMC transmits or receives sampling clock [8:0] BMC_CLK_CNT counters. 21.2.4 PD Control Register (R32_USBPD_CONTROL) Offset address: 0x04...
  • Page 303 CH32L103 Reference Manual https://wch-ic.com TX_SEL4 TX_SEL3 TX_SEL2 Reserved TX_SEL1 Name Access Description Reset value Select the K-CODE4 type in PD transmitting mode: 00: SYNC2; [7:6] TX_SEL4 01: SYNC3; 1x: RST2. Select the K-CODE3 type in PD transmitting mode: 00: SYNC1;...
  • Page 304 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [7:0] DATA_BUF DMA cache data 21.2.12 PD Interrupt Flag Register (R8_STATUS) Offset address: 0x09 IF_TX_END IF_RX_RESET IF_RX_ACT IF_RX_BYTE IF_RX_BIT BUF_ERR BMC_AUX Name Access Description Reset value Transfer completed interrupt flag, write 1 clear IF_TX_END 0, write 0 invalid.
  • Page 305 CH32L103 Reference Manual https://wch-ic.com [8:0] BMC_BYTE_CNT Byte counter. 21.2.14 Port Control Register (R32_USBPD_PORT) Offset address: 0x0C Name [15:8] R16_PORT_CC2 [7:0] R16_PORT_CC1 21.2.15 CC1 Port Control Register (R16_PORT_CC1) Offset address: 0x0C Reserved CC1_CE CC1_LVE CC1_PU CC1_PD PA_CC1_AI Name Access Description Reset value...
  • Page 306 CH32L103 Reference Manual https://wch-ic.com independent of GPIO and can be controlled separately, but some package forms of the chip do not have built-in Rd, refer to the selection table in CH32L103DS0.PDF. PA_CC1_AI The CC1 port comparator simulates input. 21.2.16 CC2 Port Control Register (R16_PORT_CC2)
  • Page 307 CH32L103 Reference Manual https://wch-ic.com do not have built-in Rd, specifically refer to the selection table in CH32L103DS0.PDF PA_CC2_AI The CC2 port comparator Analog input. 21.2.17 DMA Cache Address Register (R32_USBPD_DMA) Offset address: 0x10 Name [31:15] Reserved [15:0] R16_DMA 21.2.18 PD Buffer Start Address Register (R16_DMA)

  • Page 308: Chapter 22 Controller Area Network (Can)

    CH32L103 Reference Manual https://wch-ic.com Chapter 22 Controller Area Network (CAN) Controller Area Network is a high-performance communication protocol for serial data communication. The CAN controller provides a complete implementation of the CAN protocol, supporting CAN protocols 2.0A and 2.0B. The...

  • Page 309: Loopback Mode

    CH32L103 Reference Manual https://wch-ic.com To enter the normal mode from sleep mode, the SLEEP bit of CAN_CTLR must be cleared 0, and when the SNAK bit of register CAN_STATR is automatically cleared 0, it will enter normal mode. Figure 22-1 CAN operating mode switch...
  • Page 310 CH32L103 Reference Manual https://wch-ic.com mode is usually used for the closed self-test of the CAN controller. In this mode, it has no effect on the CAN bus, the RX pin is disconnected from the bus, and the TX pin is set to a recessive bit.
  • Page 311 CH32L103 Reference Manual https://wch-ic.com state, the abort request may succeed (stop sending) or fail (sending complete), and the result can be queried by the TXOK bit in the CAN_TSTATR register. 22.5.4 Time-based Trigger Mode When the traditional CAN communication bus is busy, it is easy to cause low-priority messages to be blocked for a long time, and even cannot meet the requirements of its time limit.

  • Page 312: Error Handling

    CH32L103 Reference Manual https://wch-ic.com Figure 22-3 Receive FIFO state switching diagram Valid message Valid message Valid message Valid message Registered Registered Registered received received received received Empty Overflow FMP=00b FMP=11b FMP=01b FMP=11b FMP=10b FOVR=0 FOVR=1 Release Mailbox Release Mailbox Release Mailbox...

  • Page 313: Bit Timing

    CH32L103 Reference Manual https://wch-ic.com Figure 22-4 CAN error state switch diagram When TEC or REC > 127 Error active Error passive status state When TEC or REC < 128 When TEC > When the bus appears 128 times, 11 recessive bits...

  • Page 314: Before Adjustment

    CH32L103 Reference Manual https://wch-ic.com Figure 22-5 The jump appears in BS1 Before adjustment: After adjustment: If the SJW of figure 22-5 is 2, and the bus level jump is detected in time period 1, the length of time period 1 needs to be extended, with a maximum extension of SJW, thus delaying the position of the sampling point.
  • Page 315 CH32L103 Reference Manual https://wch-ic.com Errors and state change interruptions are caused by errors, arousal, and sleep events. Figure 22-7 CAN interrupt logic diagram R32_CAN_INTENR Send interrupt TMEIE RQCP0 R32_CAN_TSTART RQCP1 RQCP2 FMPIE0 FMP0 FIFO0 sends interrupts FFIE0 R32_CAN_RFIF00 FULL0 FOVIE0...

  • Page 316: Register Description

    CH32L103 Reference Manual https://wch-ic.com count Note: the FIFO depth received by the FD frame is 1, that is, every time the data is received to the DMA_R0/1, the software must take the data packet in the RAM in time, otherwise the data will be overwritten.
  • Page 317 CH32L103 Reference Manual https://wch-ic.com R32_CAN_TXMIR0 0x40006580 CAN Tx mailbox 0 identifier register R32_CAN_TXMDTR0 0x40006584 CAN Tx mailbox 0 data length and timestamp register R32_CAN_TXMDLR0 0x40006588 CAN Tx mailbox 0 data low register R32_CAN_TXMDHR0 0x4000658C CAN Tx mailbox 0 data high register...
  • Page 318 CH32L103 Reference Manual https://wch-ic.com The time trigger mode is mainly used with the TTCAN protocol. Offline automatic exit control 1: The hardware detects 11 consecutive implicit bits 128 times and automatically exits the offline state; ABOM 0: The INRQ bit of the software operation register CAN_CTLR is required to be set to 1 and then cleared to 0.
  • Page 319 CH32L103 Reference Manual https://wch-ic.com the sleep mode. Initialize mode request 1: Set to 1 to request the CAN controller to enter the initialization mode. After the current activity is completed, the controller enters the initialization mode, and the hardware sets the INAK bit of the INRQ register CAN_STATR to 1;...
  • Page 320 CH32L103 Reference Manual https://wch-ic.com sleep mode, the hardware will set it to 1. Set to 1 by software to clear to 0, and set to 0 is invalid. Error interrupt. When the ERRIE bit in the CAN_INTENR register is set to 1, an error and ERRI status change interrupt is generated.
  • Page 321 CH32L103 Reference Manual https://wch-ic.com Indicates the empty flag bit of sending mailbox 0. 1: Indicates that mailbox 0 does not have a TME0 message waiting to be sent. 0: Indicates that mailbox 0 is waiting to send a message. Mailbox number.
  • Page 322 CH32L103 Reference Manual https://wch-ic.com mailbox1 has a low arbitration priority and fails to send, this bit is automatically set to 1. Tx mailbox1 transmit OK. 1: The last transmission was successful; TXOK1 0: The last transmission failed. Set to 1 by software to clear, software write 0 is invalid.
  • Page 323 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [31:6] Reserved Reserved When the software sets this bit to 1, it releases the current mailbox message of the receiving FIFO_0, RFOM0 and automatically clears it to 0 after the release, and software write 0 is invalid.
  • Page 324 CH32L103 Reference Manual https://wch-ic.com 0: No interrupt is generated when the CAN controller generates an error. [14:12] Reserved Reserved. Last error number interrupt enable. 1: When an error is detected, the hardware updates LEC[2:0], updates the ERRI bit to 1, and LECIE triggers an error interrupt;...
  • Page 325 CH32L103 Reference Manual https://wch-ic.com 0: When FIFO_0 updates the FMP bit, and it is not 0, the FIFO_0 interrupt is not triggered. Tx mailbox empty interrupt. 1: When the Tx mailbox is empty, an interrupt is TMEIE generated; 0: No interrupt is generated when the Tx mailbox is empty.
  • Page 326 CH32L103 Reference Manual https://wch-ic.com 110: CRC error; 111: Software settings. Usually when the application software reads the error, the code name is set to 111b, and the code name update can be detected. Reserved Reserved Offline status flag. When the CAN controller enters the offline state, BOFF the hardware automatically sets it to 1;...
  • Page 327 CH32L103 Reference Manual https://wch-ic.com It defines how many minimum time units are occupied by time period 2, and the actual value is (TS2[1:0]+1). Time period 1 set value. It defines how many minimum time units are [19:16] TS1[3:0] 0011b occupied by time period 1, and the actual value is (TS1[1:0]+1).
  • Page 328 CH32L103 Reference Manual https://wch-ic.com [15:0] TIMCNT[15:0] Time-triggered count value 22.8.10 CAN Offline Recovery Error Counter (CAN_TERR_CNT) Offset address: 0x28 Reserved Reserved TX_ERR_CNT Name Access Description Reset value [31:9] Reserved Reserved Currently, the error count value is recovered [8:0] TX_ERR_CNT offline. If you modify the count value, you can recover it immediately from offline.
  • Page 329 CH32L103 Reference Manual https://wch-ic.com When transmitting FD frames, there are three ESI bits of the transmitting mailbox: 1: The software forces the sending of hidden [6:4] USER_ESI_B ESI bits. 0: Automatic hardware configuration, send explicit ESI when the error is active, and...
  • Page 330 CH32L103 Reference Manual https://wch-ic.com when resynchronization is implemented, the actual value is FD_SJW+1 and the range can be set from 1 to 4 minimum time units. 22.8.13 CANFD Transmit Delay Compensation Register (CANFD_TDCT) Offset address: 0x34 Reserved Reserved TDC_FILTER Reserved...
  • Page 331 CH32L103 Reference Manual https://wch-ic.com Reser DMA_ADDR_T0 Name Access Description Reset value [31:15] Reserved Reserved The FD frame sends the transmit buffer [14:0] DMA_ADDR_T0 corresponding to mailbox 0. The address must be 4-byte aligned. 22.8.16 CANFD DMA Transmit Mailbox 1 Cache Register (CANFD_DMA_T1)
  • Page 332 CH32L103 Reference Manual https://wch-ic.com Reser DMA_ADDR_R0 Name Access Description Reset value [31:15] Reserved Reserved FD frame receive FIFO0 corresponds to the [14:0] DMA_ADDR_R0 receive buffer, the address must be 4-byte aligned. 22.8.19 CAN Tx Mailbox Identifier Register (CAN_TXMIRy) (y=0/1/2) Offset address: 0x180,0x190,0x1A0...
  • Page 333 CH32L103 Reference Manual https://wch-ic.com The 16-bit timer value used to send the message [31:16] TIME[15:0] SOF time. [15:9] Reserved Reserved Message timestamp transmission selection flag. This bit is valid when TTCM is set to 1 and the message length is 8.
  • Page 334 CH32L103 Reference Manual https://wch-ic.com 22.8.23 CAN Rx Mailbox Identifier Register (CAN_RXMIR0) Offset address: 0x1B0 STID[10:0]/EXID[28:18] EXID[17:13] EXID[12:0] IDE RTR FDF Name Access Description Reset value STID[10:0] The upper 11 bits of a standard or extended [31:21] /EXIDH[28:18] identifier. [20:3] EXIDL[17:0] The lower 18 bits of the extended identifier.
  • Page 335 CH32L103 Reference Manual https://wch-ic.com 22.8.25 CAN Rx Mailbox Data Low Register (CAN_RXMDLR0) Offset address: 0x1B8 DATA3[7:0] DATA2[7:0] DATA1[7:0] DATA0[7:0] Name Access Description Reset value [31:24] DATA3[7:0] The data byte 3 that receives the message. [23:16] DATA2[7:0] The data byte 2 that receives the message.

  • Page 336: Chapter 23 Operational Amplifier (Opa) And Comparator (Cmp)

    CH32L103 Reference Manual https://wch-ic.com Chapter 23 Operational Amplifier (OPA) and Comparator (CMP) The module consists of an independently configurable operational amplifier (OPA or PGA) and three independently configurable voltage comparators (CMP). The operational amplifier (OPA or PGA) supports gain selection or can be used as a voltage comparator.
  • Page 337 CH32L103 Reference Manual https://wch-ic.com PB15 PB14 PSEL1 MODE1 PB11 0000 OPA1 0001 FB_EN1 PB10 0010 NSEL1 0011 0100 391K 0101 12.6K 55.9K 26.1K 6.2K PB10 0110 1001 0111 1000 1010 23.2.2 OPA Positive Input Polling Each OPA's P terminal can be selected from OPA_P0/OPA_P1/OPA_P2/OPA_P3/OPA_P4/OPA_P5, and the polling function of the OPA can be realized by selecting OPA_P0/OPA_P1/OPA_P2/OPA_P3/OPA_P4/OPA_P5 sequentially at regular intervals to take turns to select all P terminals;...
  • Page 338 CH32L103 Reference Manual https://wch-ic.com high. 23.2.4 OPA Reset After enabling the OPA function, set RST_EN=1 to turn on the OPA reset function, and the system is reset when the OPA output is high. 23.2.5 OPA Brake The brake signal source can be selected by setting the BKIN_EN bit in the OPA_CFGR1 register. When BKIN_EN=1, the brake source of TIM1 comes from OPA, and at this time, it is invalid to use the IO pin for braking;...

  • Page 339: Register Description

    CH32L103 Reference Manual https://wch-ic.com The required conditions when using external interrupt wake-up are: 1) Configure the event enable bit (EXTI_EVENR) of the corresponding external interrupt channel; 2) Configure the comparator output level trigger edge, selecting rising edge trigger, falling edge trigger or double edge trigger;...
  • Page 340 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value Reserved Reserved Interrupt flag for end of OPA polling interval: 0: Invalid; IF_CNT 1: End of polling interval. Write 0 to clear, write 1 to invalidate. Reserved Reserved Interrupt flag for polling to OPA1 output high: 0: Invalid;...
  • Page 341 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value Reserved Reserved Query the number of positive ends polled by OPA1: 000: 01P0 001: 01P1 POLL1_CNT[2:0 010: 01P2 [14:12] 011: 01P3 100: 01P4 101: 01P5 Other: Reserved Configure the number of positive ends to be polled by...
  • Page 342 CH32L103 Reference Manual https://wch-ic.com 0010: PB10 0011: PA5 0100：PA1 0101: PA7 0110: PB10, PGA mode, internal gain of 32, feedback resistor 391kΩ 0111: PGA mode, no negative input channel, internal gain 8 1000: PGA mode, no negative input channel, internal gain 16...
  • Page 343 CH32L103 Reference Manual https://wch-ic.com Name Access Description Reset value [31:26] Reserved Reserved CMP wake-up level configuration: 00: Disables the CMP wake-up function; 01: Both rising and falling edges of the output of the comparator wake up the system; [25:24] WKUP_MD[1:0] 10: Wake-up system on the rising edge of the output of the comparator;...
  • Page 344 CH32L103 Reference Manual https://wch-ic.com 00: Output channel is PB5 01: Output channel is PB11 1x: Output channel is internal channel TIM2_CH2 CMP2 enable 0: Disable CMP2 1: Enable CMP2 Reserved Reserved CMP1 low-power switch 0: Off 1: On, 3.2μA CMP1 comparator hysteresis function selection...

  • Page 345: Chapter 24 Flash Memory And User Option Bytes

    CH32L103 Reference Manual https://wch-ic.com Chapter 24 Flash Memory and User Option Bytes 24.1 Flash Memory Organization The flash memory organization inside the chip is as follows: Table 24-1 Flash memory organization Block Name Address range Size (byte) Page 0 0x0800 0000 – 0x0800 00FF Page 1 0x0800 0100 –...
  • Page 346 CH32L103 Reference Manual https://wch-ic.com Name Access address Description Reset value R32_FLASH_ACTLR 0x40022000 Access control register 0x00000000 R32_FLASH_KEYR 0x40022004 FPEC key register 0xXXXXXXXX R32_FLASH_OBKEYR 0x40022008 OBKEY register 0xXXXXXXXX R32_FLASH_STATR 0x4002200C Status register 0x00000000 R32_FLASH_CTLR 0x40022010 Control register 0x00008080 R32_FLASH_ADDR 0x40022014 Address register...
  • Page 347 CH32L103 Reference Manual https://wch-ic.com OBKEYR[31:16] OBKEYR[15:0] Name Access Description Reset value Selection word key for entering a selection word key to disarm OBWRE. [31:0] OBKEYR[31:0] KEY1 = 0x45670123; KEY2 = 0xCDEF89AB. (Note: FLASH needs to be unlocked first) 24.3.4 Status Register (FLASH_STATR)
  • Page 348 CH32L103 Reference Manual https://wch-ic.com BER3 Reserved Reserved FTER FTPG Reser EOPI Reser ERRI Reser Reser OBER Reserved MER PER KEIE Name Access Description Reset value [31:25] Reserved Reserved BER32 Perform block erase 32KB [22:20] Reserved Reserved BUFRST BUF reset operation...
  • Page 349 CH32L103 Reference Manual https://wch-ic.com means that FPEC and FLASH_CTLR are locked unwritable. After the correct unlock sequence is detected, the hardware clears this bit as'0'. After an unsuccessful unlock operation, the bit will not change until the next time the system is reset.
  • Page 350 CH32L103 Reference Manual https://wch-ic.com Configuring CAN offline recovery time. 1: Recovery from offline to normal is a bit faster, CFGCANM 0: Recovery from offline to normal in accordance with the CAN protocol [6:5] Reserved Reserved USER STANDY_ System reset control in Standby mode, active low.

  • Page 351: Read Operation

    CH32L103 Reference Manual https://wch-ic.com Quick Program/Erase mode: KEY1 = 0x45670123; KEY2 = 0xCDEF89AB. 24.4 Flash Operation Procedure 24.4.1 Read Operation Direct addressing is in the general address space, and the user can access the content of the flash memory module and get the corresponding data through any read operation of 8/16/32-bit data.
  • Page 352 CH32L103 Reference Manual https://wch-ic.com Lock" operation. 2) Set the PEG bit in the FLASH_CTLR register to ‘1’ to enable the standard page erasure mode. 3) Write the page heading address of the page to be erased to the FLASH_ADDR register.
  • Page 353 CH32L103 Reference Manual https://wch-ic.com 24.4.5 Main Memory Fast Programming The fast programming (256 bytes) is made according to the page. 1) Check the LOCK bit of the FLASH_CTLR register. If it is' 1blank, you need to perform the "unlock flash"...
  • Page 354 CH32L103 Reference Manual https://wch-ic.com 2) Check the FLASH_CTLR register FLOCK bit, if it is 1, you need to perform a "fast programming mode unlock" operation. 3) Check the BSY bit of the FLASH_STATR register to confirm that there are no other programming operations in progress.
  • Page 355 CH32L103 Reference Manual https://wch-ic.com [7:6] Reserved Reserved Configure CAN offline recovery time: 1: It's faster to get back to normal offline. CFGCANM 0: Restore from offline to normal and comply with CAN protocol [4:3] Reserved Reserved System reset control in Standby mode: STANDYR 1: Do not enable, enter Standby mode system does not reset.
  • Page 356 CH32L103 Reference Manual https://wch-ic.com 2) Check the FLASH_CTLR register FLOCK bit, if it is' 1percent, you need to perform a "quick programming mode unlock" operation. 3) Check the BSY bit of the FLASH_STATR register to confirm that there are no other programming operations in progress.
  • Page 357 CH32L103 Reference Manual https://wch-ic.com 2) The user chooses words to program and writes the correct RDPR code 0xA5 to remove the read protection of the flash memory. (This step will first cause the system to automatically erase the entire piece of flash memory.).

  • Page 358: Chapter 25 Extended Configuration (Exten)

    CH32L103 Reference Manual https://wch-ic.com Chapter 25 Extended Configuration (EXTEN) 25.1 Extended Configuration The system provides an EXTEN extension configuration unit (EXTEN_CTR register). The unit uses an HB clock and performs a reset action only when the system is reset. It mainly includes the following extended control bit...
  • Page 359 CH32L103 Reference Manual https://wch-ic.com LKUPRST bit when lock-up occurs. 0: Disable. Reserved Reserved HSI clock: (Only can be written when PLL is disabled.) HSIPRE 1: HSI clock selected as PLL input clock. 0: HSI clock divided by 2 selected as PLL input clock.

  • Page 360: Chapter 26 Debug Support (Dbg)

    CH32L103 Reference Manual https://wch-ic.com Chapter 26 Debug Support (DBG) 26.1 Main Features This register allows the MCU to be configured in the debug state. Includes:  Counters supporting Independent Watchdog (IWDG)  Counters supporting Window Watchdog (WWDG)  Counter supporting timer ...
  • Page 361 CH32L103 Reference Manual https://wch-ic.com Timer 1 debug stop bit. The counter stops when the core enters the debug state. TIM1_STOP 1: Timer 1's counter stops working. 0: Timer 1's counter is still working normally. SMBUS timeout mode debug stop bit. Stops SMBUS I2C2_SMBUS_ timeout mode when the core enters debug state.
  • Page 362 CH32L103 Reference Manual https://wch-ic.com Therefore, the software must reconfigure the clock control system to start PLL, crystal oscillator and so on. Debug sleep mode bits. 1: (FCLK on, HCLK on) in sleep mode, both the FCLK and HCLK clocks are provided by the previously configured system clock.

  • Page 363: Chapter 27 Electronic Signature (Esig)

    CH32L103 Reference Manual https://wch-ic.com Chapter 27 Electronic Signature (ESIG) Electronic Signature contains chip identification information: Flash memory area capacity and unique identification. It is burned into the system storage area of the memory module by the manufacturer when leaving the factory, and can be read through SWD (SDI) or application code.
  • Page 364 CH32L103 Reference Manual https://wch-ic.com 27.2.3 UID Register (ESIG_UNIID2) U_ID[63:48] U_ID[47:32] Name Access Description Reset value [31:0] U_ID[63:32] Bits 32-63 of the UID. 27.2.4 UID Register (ESIG_UNIID3) U_ID[95:80] U_ID[79:64] Name Access Description Reset value [31:0] U_ID[95:64] Bits 64-95 of the UID.

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