Pfic Interrupt Pending Status Register 2; Pfic Interrupt Priority Threshold Configuration Register; Pfic Interrupt Configuration Register (Pfic_Cfgr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
6.5.2.4 PFIC interrupt pending status register 2 (PFIC_IPR2)
Offset address: 0x24
31 30 29 28
15 14 13 12
Bit Name
[31:7] Reserved
[6:0] PENDSTA32_38
6.5.2.5 PFIC interrupt priority threshold configuration register (PFIC_ITHRESDR)
Offset address: 0x40
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name
[31:8] Reserved
[7:0] THRESHOLD

6.5.2.6 PFIC interrupt configuration register (PFIC_CFGR)

Offset address: 0x48
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:16] KEYCODE
[15:8] Reserved
7 RESETSYS
V1.3
27 26 25
11 10 9
Reserved
Access
RO Reserved
32#-38# Interrupt current pending status.
RO 1: The current number break is pending.
0: The current number break is not pending.
Reserved
Access
RO Reserved
Interrupt priority threshold setting value.
The interrupt priority value lower than the
current setting value, when hung, does not
perform interrupt service; this register is 0
RW
means the threshold register function is
invalid.
[7:6]: priority threshold.
[5:0]: reserved, fixed to 0, write invalid.
27 26 25
KEYCODE[15:0]
11 10 9
Access
Corresponding to different target control bits, the
corresponding security access identification data needs
to be written simultaneously in order to be modified,
WO and the readout data is fixed to 0.
KEY1 = 0xFA05.
KEY2 = 0xBCAF.
KEY3 = 0xBEEF.
RO Reserved
System reset (simultaneous writing to KEY3). Auto
WO
clear 0.
24 23 22 21
Reserved
8 7 6 5
Description
Description
24 23 22 21
8 7 6 5
RESE
TSYS
Description
39
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20 19 18 17
4 3 2 1
PENDSTA[38:32]
Reset value
0
0
THRESHOLD[7:0]
Reset value
0
0
20 19 18 17
4 3 2 1
Reserved
Reset value
0
0
0
16
0
16
0