WCH CH32V003 Series Reference Manual page 25

CH32V003 Reference Manual
28 SFTRSTF
27 PORRSTF
26 PINRSTF
25 Reserved
24 RMVF
[23:2] Reserved
1 LSIRDY
0 LSION
Note: Except for the reset flag which can only be cleared by power-on reset, others are cleared by system Reset.
V1.3
occurs; cleared by software writing of the RMVF bit.
Software reset flag.
1: Software reset occurs.
RO 0: No software reset occurs.
Set to 1 by hardware when a software reset occurs;
software write RMVF bit cleared.
Power-up/power-down reset flag.
1: Power-up/power-down reset occurs.
RO 0: No power-up/power-down reset occurs.
Set to 1 by hardware when power-up/power-down reset
occurs; cleared by software writing of RMVF bit.
External manual reset (NRST pin) flag.
1: Occurrence of NRST pin reset.
RO 0: No NRST pin reset occurs.
Set to 1 by hardware when NRST pin reset occurs; cleared
by software writing of RMVF bit.
RO Reserved
Clear reset flag control.
RW 1: Clear the reset flag.
0: No effect.
RO
Reserved。
Internal Low Speed Clock (LSI) Stable Ready flag bit (set
by hardware).
1: Stable internal low-speed clock (128KHz).
RO
0: The internal low-speed clock (128KHz) is not stable.
Note: After the LSION bit is cleared to 0, the bit requires 3
LSI cycles to clear 0.
Internal low-speed clock (LSI) enable control bit.
RW 1: Enable the LSI (128KHz) oscillator.
0: Disable the LSI (128KHz) oscillator.
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