Adc Delayed Data Register (Adc_Dlyr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
15 14 13 12
Bit Name
[31:0] DATA

9.3.15 ADC Delayed data register (ADC_DLYR)

Offset address: 0x50
31 30 29 28
15 14 13 12
Reserved
Bit Name
[31:10] Reserved
9 DLYSRC
[8:0] DLYVLU
V1.3
11 10 9 8
DATA[15:0]
Access
Rule channel conversion data (data left-aligned or right-
RO
aligned)
27 26 25 24
Reserved
11 10 9 8
DLYS
RC
Access
RO Reserved
External trigger source delay selection
RW 0: Rule channel external trigger delay
1: Injection channel external trigger delay
External trigger delay data, delay time configuration, unit:
RW
ADC clock cycle
7 6 5
Description
23 22 21
7 6 5
DLYVLU
Description
85
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4 3 2 1
Reset
value
20 19 18 17
4 3 2 1
Reset
value
0
0
16
0
0
0
0