Block Diagram Of The Structure Of The Comparison Capture Channel - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Figure 10-3 Block diagram of the structure of the comparison capture channel
TI1
Filter
f
downcounter
DTS
ICF[3:0]
TIMx_CHCTLR1
Read CCR1H
S
Read CCR1L
R
CC1S[1]
CC1S[0]
IC1PS
CC1E
CC1G
TIM1_SWEVGR
ETRF
>
CNT CCR1
Output
mode
CNT = CCR1
controller
OCxREF
OCxREF
OC1CE OC1M[3:0]
TIM1_CHCTLR1
The structure block diagram of the comparison capture channel is shown in Figure 10-3. The signal is input
from the channel x pin and optionally made as TIx (the source of TI1 can be more than just CH1, see the
structure block diagram of timer 10-1), TI1 is passed through the filter (ICF[3:0]) to generate TI1F, and then
divided into TI1F_Rising and TI1F_Falling through the edge detector, these two signals are selected (CC1P)
to generate TI1FP1, TI1FP1 and TI2FP1 from channel 2 are sent together to CC1S to select to become IC1,
which is sent to the comparison capture register after ICPS dividing.
The compare capture register consists of a preload register and a shadow register, and the read/write process
operates only on the preload register. In capture mode, the capture occurs on the shadow register and is then
copied to the preload register; in compare mode, the contents of the preload register are copied to the shadow
register, and then the contents of the shadow register are compared to the core counter (CNT).
V1.3
TI1F_Rising
TI1F
Edge
TI1F_Falling
detector
CC1P/CC1NP
TIMx_CCER
TI2F_Rising
(from channel 2)
TI2F_Falling
(from channel 2)
APB Bus
MCU-peripheral interface
read_in_progress
Capture/compare preload register
capture_transfer
Input
mode
Capture/compare shadow register
Capture
Counter
To the master mode
controller
OC1REFC
OC1REF
Output Dead-time
selector generator
DTG[7:0]
TIM1_BDTR
TI1F_ED
To the slave mode controller
0
TI1FP1
01
1
IC1
TI2FP1
10
TRC
11
(from slave mode
controller)
0
CC1S[1:0] ICPS[1:0]
1
TIMx_CHCTLR1 TIMx_CCER
write_in_progress
Output
compare_transfer
mode
Comparator
0
'0'
x0 1
01
OC1_DT
CC1P
11
TIM1_CCER
OC1N_DT
11
0
10
'0'
0x
1
CC1NE CC1E CC1NP
TIM1_CCER
TIM1_CCER
90
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Divider
/1,/2,/4,/8
CC1E
Write CCR1H
S
Write CCR1L
R
CC1S[1]
CC1S[0]
OC1PE
OC1PE
UEV
TIM1_CHCTLR1
(from time
base unit)
Output
OC1
enable
circuit
Output
OC1N
enable
circuit
CC1NE CC1E TIM1_CCER
MOE OSSI OSSR
TIM1_BDTR