Dma Control Register (Tim1_Dmacfgr) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
14 AOE
13 BKP
12 BKE
11 OSSR
10 OSSI
[9:8] LOCK
[7:0] DTG

10.4.19 DMA Control register (TIM1_DMACFGR)

Offset address: 0x48
15 14 13 12
Reserved
V1.3
Auto output enable.
1: the MOE can be set by software or set in the next
RW
update event.
0: MOE can only be set by software.
The brake input polarity setting bit.
1: brake input active high.
0: Brake input is active low.
RW
Note: When LOCK level 1 is set, this bit cannot be
modified. A write to this bit requires an APB clock
before it can take effect.
Brake function enable bit.
1: Turn on the brake input.
0: Brake input is disabled.
RW
Note: When LOCK level 1 is set, this bit cannot be
modified. A write to this bitrequires an APB clock
before it can take effect.
1: when the timer is not working, once CCxE=1 or
CCxNE=1, first turn on OC/OCN and outputinvalid
level, then set OCx, OCxN enable output signal=1.
RW 0: When the timer is not operating, OC/OCN output is
disabled.
Note: When LOCK level 1 is set, this bit cannot be
modified.
1: when the timer is not operating, once CCxE = 1 or
CCxNE = 1, OC/OCN first outputs its idle level, then
OCx, OCxN enable output signal = 1.
RW 0: When the timer is not operating, OC/OCN output is
disabled.
Note: When LOCK level 1 is set, this bit cannot be
modified.
Lock the function setting field.
00: Disable the locking function.
01: lock level 1, no DTG, BKE, BKP, AOE, OISx and
OISxN bits can be written.
10: Lock level 2, where the bits in lock level 1 cannot
RW be written, nor the CC polarity bits, nor the OSSR and
OSSI bits.
11: Lock level 3, cannot write to the bits in lock level 2,
and cannot write to the CC control bits.
Note: After system reset, the LOCK bit can only be
written once and cannot be modified again until reset.
Deadband setting bits that define the duration of the
deadband between complementary outputs.
Assume that DT denotes its duration.
DTG[7:5]=0xx=>DT=DTG[7:0]*Tdtg, Tdtg=TDTS；
DTG[7:5]=10x=>DT=(64+DTG[5:0])*Tdtg,
RW
2*TDTS;
DTG[7:5]=110=>DT=(32+DTG[4:0])*Tdtg, Tdtg =8
×TDTS;
DTG[7:5]=111=>DT=(32+DTG[4:0])*Tdtg, Tdtg =16
*TDTS.
11 10 9 8
DBL[4:0]
110
7 6 5 4
Reserved
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0
0
0
0
0
0
Tdtg=
0
3 2 1 0
DBA[4:0]