Pfic Interrupt Pending Setup Register 2 (Pfic_Ipsr2); Pfic Interrupt Pending Clear Register 1 (Pfic_Ipsr1) - WCH CH32V003 Series Reference Manual

CH32V003 Reference Manual
Reser PEND Rese PEND
ved SET14 rved SET12
Bit Name
[31:16] PENDSET16_31
15 Reserved
14 PENDSET14
13 Reserved
12 PENDSET12
[11:4] Reserved
[3:2] PENDSET2_3
[1:0] Reserved

6.5.2.16 PFIC interrupt pending setup register 2 (PFIC_IPSR2)

Offset address: 0x204
31 30 29 28
15 14 13 12
Bit Name
[31:7] Reserved
[6:0] PENDSET32_38

6.5.2.17 PFIC interrupt pending clear register 1 (PFIC_IPSR1)

Offset address: 0x280
31 30 29 28
15 14 13 12
PEND
Reser Rese PEND
RESET
ved rved RESET12
14
Bit Name
[31:16] PENDRESET16_31
V1.3
Access
16#-31# interrupt pending setting.
WO 1: current numbered interrupt hang.
0: No effect.
RO Reserved
14# Interrupt hang setting.
WO 1: current numbered interrupt hang.
0: No effect.
RO Reserved
12# Interrupt hang setting.
WO 1: current numbered interrupt hang.
0: No effect.
RO Reserved
2#-3# interrupt pending setting.
WO 1: current number break hang.
0: No effect.
RO Reserved
27 26 25
11 10 9
Reserved
Access
RO Reserved
32#-38# interrupt pending setting.
WO 1: current number break hang.
0: No effect.
27 26 25
PENDRESET[31:16]
11 10 9
Access
16#-31# interrupt hang clear.
1: The current numbered interrupt clears
WO
the pending state.
0: No effect.
Reserved
Description
24 23 22 21
Reserved
8 7 6 5
Description
24 23 22 21
8 7 6 5
Reserved
Description
43
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PEN PEN
D D Reserved
SET3 SET2
Reset value
0
0
0
0
0
0
0
0
20 19 18 17
4 3 2 1
PENDSET[38:32]
Reset value
0
0
20 19 18 17
4 3 2 1
PEND PEND
RESE RESE Reserved
T3 T2
Reset value
0
16
0
16
0